POST CORRELATOR INTEGRATOR

SYSTEM DESIGN

DOCUMENT NUMBER:

PROJECT:	RTD ERB4062PL975013

ISSUE:	DRAFT

DATE:

i.	AMENDMENT RECORD

ii.	TABLE OF CONTENTS

i.	AMENDMENT RECORD	i

ii.	TABLE OF CONTENTS	ii

1	INTRODUCTION	1

1.1	System Design	1

1.2	Documentation References	1

1.3	Definitions of Terms	1

2	SYSTEM ARCHITECTURE	1

2.1	Introduction	1

2	Identification of processing units	3

2.1	The real-time system	3

2.2	The processor board	4

2.3	The recording board	4

3	SYSTEM COMPONENTS	4

3.1	Real-Time system	4

3.2	Processing board	5

3.3	Recording board	5

iii.	INTRODUCTION	6

2	REAL TIME SYSTEM	6

3	PROCESSING BOARD	6

4	DATA RECORDER BOARD	6

5	PCI control board	7

5.1	VMEbus data transporter	7

5.2	VMEbus interrupter	9

5.3	VMEbus register (0)	10

1	INTRODUCTION

1.1	System Design

System design is the high level strategy for solving the problem and building a solution. System design includes decisions about the organization of the system into subsystems, the allocation of subsystems to hardware and software components. The overall organization of a system is called the system architecture.

In the system design high-level decisions are made about the overall architecture. During system design, the target system is organized into subsystems based on both the analysis structure and the proposed architecture.

1.2	Documentation References

1.3	Definitions of Terms

PCI	Post Correlator Intergrator

PCI unit	Subpart of the PCI residing in a VME rack inside the correlator crate.

PCI segment	Smallest entity providing PCI functionality. It consists of a data processing board and a data recorder board with a SCSI connection. It handles input from four correlator boards.

CCC / C3	Correlator Control Computer

DDD / D3

PMC	PCI Mezzanine Connector

2	SYSTEM ARCHITECTURE

2.1	Introduction

Based on the requirement analysis a possible solution for the PCI is to separate it into several independent units. Because the correlator consists of eight independent correlator segments, an obvious choice is to separated the PCI in eight independent PCI segments. In this case each PCI segment has to handle input coming from four correlator boards. The output from each PCI segment will be a SCSI interface for connecting to a general SCSI tape device.

Because two correlator segments reside in one correlator crate, it must be possible for two PCI segments to reside in the same VME-rack at the bottom of a correlator rack.

Building a PCI segment with four C40 communication ports as inputs has the advantage that there are commercially available DSP boards which can handle four C40 comm ports. Accompanied by a board or module providing a SCSI interface this could provide all the processing power for a PCI segment. By connecting one correlator segment to a DSP board, it is also possible to combine correlator products from different correlator boards (more lags for fringes). Furthermore the output data rate is kept to an acceptable limit. The aggregated data input rate for a PCI segment is about 40 MB/s. With an reduction ratio of 4 this could meet the 10 MB/s storage transfer rate for a removable tape device.

After researching available hardware it is found that a one board solution is not feasible for a PCI segment, i.e. there is no suitable hardware available integrating processing power and a SCSI controller on one VME board. A feasible solution is to separate the PCI segment into a processing board and a data recorder board. The advantage of this solution is that there is better separation between the data processing and the recording functionality.

Available hardware options also showed that the connection between processing board and recorder board is best performed by C40 communication ports. This is due to fact that C40 communications ports are required for input from the correlator boards, The advantage of using a data recorder board with four C40 communication ports as input is that it could be connected directly to the correlator segment. This is especially useful during development, data storage can be developed independent from the data processing.

Such a PCI segment should reside in a VME crate (PCI unit). The system controller for the PCI unit should be a real-time system, preferably the same as used in the correlator units. This implementation results in the following top level architecture model.

For the entire PCI (or related units) the following top-level subsystems can be distinguished;

C3

D3

correlator board

real-time system

processing board

recording board

Tape device

All of these subsystems have processing power of their own, except for the Tape device. C3, D3 and the correlator board are not an integral part of the PCI, but are used here to give an environmental reference for the PCI.

Besides these hardware elements there are also some external events that influence the post correlation process.

BOCF interrupt

SYSTICK interrupt

These events are VMEbus interrupts on the correlator VMEbus. These are generated by the Control board in the correlator. The PCI control board will receive the correlator BOCF and SYSTICK signal and regenerates the interrupts on the VMEbus of the PCI.

A subsystem is not an object nor a function but a package of classes, associations, operations, events, and constraints that are interrelated and that have a reasonably well-defined and small interface with other subsystems. A subsystem is usually identified by the services it provides. Each subsystem has a well-defined interface to the rest of the system. The interface specifies the form of all interactions and the information flow across subsystem boundaries but does not specify how the subsystem is implemented internally. Each subsystem can then be designed independently without affecting the others.

Subsystems should be defined so that most interactions are within subsystems, rather than across subsystem boundaries, in order to reduce the dependencies among the subsystems. Each subsystem may in turn be decomposed into smaller subsystems of its own. The lowest level subsystems are called modules.

Within the correlation process (with respect to the post correlator) the following hardware components can be distinguished;

C3

D3

real-time system

correlator segment

processor board

recording board.

Besides these hardware elements there are also some external events that influence the post correlation process.

BOCF interrupt

SYSTICK interrupt

These events are VMEbus interrupts on the correlator VMEbus. These are generated by the Control board in the correlator. The PCI control board will receive the correlator BOCF and SYSTICK signal and regenerates the interrupts on the VMEbus of the PCI.

2	Identification of processing units

2.1	The real-time system

The software running on the real-time system will be mainly the same as the software running on the real-time system in the correlator. There might however be some additional configuration software required.

On of the tasks the real-time system performs is to configure and control the processing boards. The processors on the processing board will receive the same information as the correlator boards in the correlator.

On the real-time system are several tasks running.

Message server

Message processor	the message processor examines the messages one-by-one at nominally each SYSTICK interval

Application process

data server

2.2	The processor board

The processor board includes four C6x processors for processing the correlated data. These processors are interconnected using bidirectional FIFO's. Each processor has a private data bus with application memory, data memory, dual port memory and FIFO's connected to it. The private also gives access to the boards global bus.

On the boards global bus there is global SRAM, NV RAM and boot/user flash memory. The board boot from the 8 Mbs of global bus resident FLASH EEPROM. After this it will be required to load a RTOS and start the tasks running.

2.3	The recording board

The recorder boards contain two PMC modules, one C40 module and a SCSI module. The C40 board is the only board with processing power. It will directly control the SCSI controller. It does however requires information of the real-time system telling which channel to expect data from and when to start and stop a data recording. With respect to controlling the SCSI module it does have to support the sequential tape support of the SCSI protocol.

Basically the C40 has to do is find the last written position on tape. Collect data coming in through the C40 communication ports and starts writing it to tape. Until the real-time system tells him to stop.

3	SYSTEM COMPONENTS

In this chapter I want a description of the system component, which boards are used, what are the resources on these boards and what are the hardware interfaces with other boards.

3.1	Real-Time system

For the System Controller in the VME rack is a HP model 743 real-time system used. This Real-Time system is the interface between two PCI segments and the CCC and the DDD. Its main tasks are to boot the two PCI segments inside the VME rack and to configure the PCI segments for operation and to acknowledge the VME interrupts on the VME bus. These interrupts perform task scheduling and synchronization in the real-time software. These interrupts are generated in the control board in the correlator rack. It has to be checked if a proper interrupt acknowledge can be performed.

Qty	part number	description
1	W-A4261A	HP 9000 Mdl 743rt VMEbus Single Board Computers

3.2	Processing board

The main tasks for the processor board are to receive the data coming from the correlator boards. Process this data according to its configuration. The processed data is passed on to the recorder board via C40 communication ports.

Qty	part number	description
1	Pentek 4291

full quad option	Quad TMS320C6701 processor VME board
2	Pentek 6223	'C40 Comm port Adapter VIM-2 Module

3.3	Recording board

Qty	part number	description
1	M20	VMETRO Midas 20 PMC carrier
1	Pentek 7110	Single 'C44 Coprocessor PMC module
1	SCSI875-DF	SciTech SCSI-2 PMC controller

VME-Rack

Geveke electronics

postbus 652

1000 AR Amsterdam

tel: 020-5861595

fax: 020-5861985

prototype VME rack 160 mm

Qty	part number	description	price / qty	total
1	20817-032	Printkaartrek 6HE ten behoeve van Eurokaart 160 mm diep
2	30817-031	Dekplaat 6HE, geeloxeerd
2	30819-594	Schroefdraadstrip M2,5mm
4	60817-061	Isoleerstrip
40	60817-103	Printkaartgeleider ten behoeve van Eurokaart 160 mm diep
1	23000-420

23030-058	VME backplane J1/J2

VME backplane J1/J2 dubbelle connectoren
price : Dfl 2500,-

mulder-hardenberg BV

Westerpark 1a

2012 JL Haarlem

Power supply

Qty	part number	description	price / qty	total
1	137-010000	VERO - TRIVOLT PO500	fl 1688,-	fl 1688,-

iii.	INTRODUCTION

Operating environment for the Post Correlator Integrator

PCI	Post Correlator Intergrator

PCI unit	Subpart of the PCI residing in a VME rack inside the correlator crate.

PCI segment	Smallest entity providing PCI functionality. It consists of a data processing board and a data recorder board with a SCSI connection. It handles input from four correlator boards.

What is actually considered as being the PCI? The existing architecture has the following parts; the correlator, the CCC and the DDD. From the CCC and DDD point of view is the correlator constructed out of four correlator segments. The inputs for the PCI coming from the 32 correlator boards is obvious. If the actual operators at the CCC and the DDD are considered as the actual inputs to the system, than the CCC and DDD software is part of the PCI project. This seems a too general approach for the PCI project. A second approach would be to consider the CCC and the DDD as inputs to a PCI unit. This reduces the PCI project to smaller proportions leaving the CCC and the DDD to access four independent PCI units. A second consideration is the role of the System Controller that is part of the PCI segment.

2	REAL TIME SYSTEM

For the System Controller in the VME rack is a HP model 743 real-time system used. This Real-Time system is the connection between the PCI unit and the CCC and the DDD. Its main tasks are to boot the two PCI segments inside the VME rack and to configure the PCI segments for operation and to acknowledge the VME interrupts on the VME bus. These interrupts perform task scheduling and synchronization in the real-time software. These interrupts are generated in the control board in the correlator rack. It has to be checked if a proper interrupt acknowledge can be performed.

3	PROCESSING BOARD

The main tasks for the processor board are to receive the data coming from the correlator boards. Process this data according to its configuration. The processed data is passed on to the recorder board via C40 communication ports.

4	DATA RECORDER BOARD

The data recorder board main task is to convert four C40 communication ports into one SCSI output. This is created by two PMC modules. One PMC C40 comm port bridge module and a PMC SCSI controller. The C40 module can act as master on the PMC bus and program the SCSI controller directly. Therefor these modules can reside on a simple VME carrier board with no additional processing power.

(Based on module documentation, not confirmed by Pentek)

On the C40 module the following tasks need to be performed. Data collecting from four C40 comm ports, programming the SCSI controller and transferring the data to the SCSI controller.

The PCI modules need to be configured and booted by the real-time system. After this the modules are supposed to operated autonomously.

5	PCI control board

The PCI control board is a largely reduced version of the EVNFRA control board. Its only use is to regenerated the interrupts for the BCOF and the SYSTICK. Compared to the EVNFRA control board only the VMEbus module of this board is needed. It must however be checked if there are other register expected to be present on the control board.

It might be possible to just take the VMEbus module from the EVNFRA control board and use this as the PCI control board. The only change required will be the addressing of the additional registers.

The VMEbus interface performs the interfacing tasks between the VMEbus and the local circuits on the board. The VMEbus interface can only act as a slave interface. It responds only to 32 bit addressing modes (A32) and is capable of handling data transfers of 32 bits wide (D32). The VMEbus interface can also act as an interrupter. There are 3 inputs available for doing interrupts. The required interrupt vector is supplied by the interface. The interrupt vector consists of 3 bits telling which interrupt source has made the interrupt and a 5 bits unique word that tells from which board in the system the interrupt is coming from.

The VMEbus interface is built up around a XILINX EPLD XC73108-15PC84. Almost the whole VMEbus interface fits in one big EPLD. The board address and base address decoding is done outside the EPLD, for a smaller and cheaper plastic package.

The VMEbus interface consists of two main parts the VMEbus data transport and the VMEbus interrupter.

5.1	VMEbus data transporter

The VMEbus interface can only act as a slave interface. It responds only to 32 bit addressing modes (A32) and is capable of handling data transfers of 32 bits wide (D32). For supporting this addressing mode different logical components are required to complete the VMEbus data transport interface.

Board address decoder

input:

BOARDA	8 bits	8 bits board address from external DIP switch

A[31:24]	8 bits	8 address lines from VMEbus

output

AMATCH1	1	active when address match occurs

This is simply an comparator identifying a correct board address.

Base address decoder

input:

BASEA	19 bits	19 bits board address from external DIP switch

A[23:5]	19 bits	19 address lines from VMEbus

output

AMATCH0	1	active when address match occurs

This is simply an comparator identifying a correct base address.

It might be required to extend this base address with address lines A[4-2] when the additional EVNFRA control board registers are not used.

A32 cycle decoder

input:

AM[5:0]	6 bits	Addres modifier bits

IACK	1	interrupt acknowledge signal from VMEbus

output

EXAMMATCH	1	active when the VMEbus cycle is a correct addressing mode and not an interrupt acknowledge cycle.

According to suggestion 2.1 of the VMEbus specification A32 slaves with D32 capability should support addressing modes : 09, 0A, 0D, and 0E

D32 cycle decoder

input:

DS0	1	data strobe

DS1	1	data strobe

A1	1	this address line should be 0 for a D32 cycle

LWORD	1

output

D32CYCLE	1	active when a D32 access occurs

The only possible D32 cycle is a quad byte read or write cycle. For quad byte cycles DS0,DS1,A1 and LWORD must be 0 (and A0 also).

Addressing lines

A01-A31	address lines

AM0-AM5	address modifierA32 slave with D32 capability should respond to address modifiers 09, 0A, 0D, 0E

DS0*	data strobe

DS1*	data strobe

LWORD*

Data lines

D01-D31

Control lines

AS*	address strobe	A falling edge on this line informs all SLAVE modules that the address is stable and can be captured.

DS0*	data strobe

DS1*	data strobe

BERR*	bus error

DTACK*

WRITE*	read/write

SUGGESTION 2.1:

Where SLAVES are manufactured with a programmed device (e.g. a PROM or a FPLA) installed in the socket, program the device so that the SLAVE responds to the following AM codes:

A16 SLAVES with D08(0), D08(EO), D16, or D32 capability: 29, 2D

A24 SLAVES with D08(0), D08(EO), D16, or D32 capability: 39, 3A, 3D, and 3E

A32 SLAVES with D08(0), D08(EO), D16, or D32 capability: 09, OA, OD, and OE

A24 SLAVES with BLT capability: 3B, 3F

A32 SLAVES with BLT capability: OB, OF

The mnemonics A16, A24, and A32 are defined in Table 2-9. The mnemonics D08(0), D08(EO), D16, D32, and BLT are defined in Tables 2-10, and 2-11.

DS0 and DS1

The functions and requirements of DS0 and DS1 are based extracted from the VMEbus specification.

2.2.4.2 DS0* And DS1*

In addition to their function in selecting byte locations for data transfer, as described in Section 2.2.1, the data strobes also serve additional functions. On write cycles, the first data strobe failing edge indicates when the MASTER has placed valid data on the data bus. On read cycles, the first rising edge tells the SLAVE when it can remove valid data from the data bus.

OBSERVATION 2.7:

VMEbus MASTERS are not permitted to drive either of the data strobes low before driving AS* low. However, due to the fact that AS* might be more heavily loaded on the backplane than the data strobes, SLAVES and LOCATION MONITORS might detect a falling edge on a data strobe, before they detect the falling edge on AS*.

PERMISSION 2.5:

VMEbus SLAVES and LOCATION MONITORS MAY be designed to capture the address when they detect a falling edge on a data strobe instead of on the falling edge

OBSERVATION 2.8:

VMEbus SLAVES and LOCATION MONITORS that capture the address on the falling edge of the data strobes) need not monitor AS*.

OBSERVATION 2.9:

In order to take full advantage of address pipelining as described in Section 2.4.2, or to perform block read and write cycles, a SLAVE should capture the address on the falling edge of AS*.

2.2.4.3 DTACK*

The SLAVE drives DTACK* low to indicate that it has successfully received the data on a write cycle. On a read cycle, the SLAVE drives DTACK* low to indicate that it has placed data on the data bus.

PERMISSION 2.6:

VMEbus SLAVES MAY be designed without a driver for BERR*.

This board can be based on the VMEbus interface of the correlator control board.

5.2	VMEbus interrupter

The VMEbus interrupter on the control board can only act as an interrupt requester. The circuit has three interrupt inputs INT[2:0] available for local circuits. The three interrupt inputs can generate one interrupt request IRQ on the VMEbus. The IRQ level is programmable to all seven IRQ levels with the control bits IRQSEL[2:0]. The three interrupt inputs can be separately disabled and enabled with the control bits ENINT[2:0]. The circuit responds only to a 32 bit interrupt acknowledge cycle (D32) and returns a 20 bit STATUS/ID on D00-D31.

A positive going edge of an interrupt INT input will latch the event. When one positive going edge is detected then one IRQ output becomes active. The IRQ level depends on the IRQSEL bits in the control register. The interrupt handler has to respond with an interrupt acknowledge cycle. When it is a 32 bit interrupt acknowledge cycle, D32ACK will be high and when the three bits code on A[3:1] corresponds to the IRQ generated then OURIACKCYCLE will be true. On the positive going edge of SYNCIACKCYC, IRQREGEN is asserted and the STATUS/ID will be put on the data lines. After another SYSCLK, when the data is stable, DTACK will be asserted on the positive going edge of DSYNCIACKCYC.

The IRQ is released by the DTACK during the interrupt acknowledge cycle. This is called an ROAK release mechanism.

During an interrupt acknowledge cycle not conform our IRQ level or when there is no IRQ at all, OURIACKCYCLE will be low, In this case an active level on IACKIN will, after a short delay, be passed to IACKOUT.

5.3	VMEbus register (0)

The VMEbus interface EPLD XILINX XC73108-15 contains a 20 bit register. This register can be read and/or writen by normal data access. The VMEbus register listens to register address 0. This register is also returned as interrupt vector as part of the interrupt acknowledge cycle. The bit assignment in this register are:

0-2	IRQSOURCE	The 3 interrupt inputs; bit 0 is the BOCF signal taken from the correlator backplane, bit 1 is the SYSTICK and bit 2 can be used for an additional interrupt. A positive edge of the input signal will set the corresponding bit. When the VMEbus interrupts are enabled, IRQSEL has another value then 0, then the bits are cleared after the interrupt acknowledge cycle. A VMEbus read do not effect those bits. When, at the other hand, the VMEbus interrupts are disabled, IRQSEL=0, then the bits are cleared after a VMEbus read.

3-7	IVECTOR	The interrupt base vector. The 5 bits of the interrupt base vector are programmable by the VMEbus. With the 3 IRQSOURCE bits these bits form an interrupt vector.

8-10	IRQSEL	The interrupt level select bits. The 3 bits determines the level of the VMEbus interrupt, IRQnr = IRQSEL0-2. The VMEbus interrupts are disabled with interrupt level 0.

11,12,13	IBOCF, ISYSTICK and IADDI	The interrupt enable bits of the interrupt inputs. The VMEbus interrupt are, for the 3 interrupt inputs separately, to enable. The status of the disabled inputs can still be read from the register. How the reset of the input takes place still depends on the IRQSEL setting.

14-19	IDENT0-5	The VMEbus interface has 6 available input lines that can be read from the VMEbus register. These lines are used for a unique identification code for the control board.