Post Correlator Integrator

These pages contain information on the Post Correlator Integrator project. This project is a result from a grant from the EC, under the TMR-LSF RTD Project, contract number ERBFMGECT 980101, Training and Mobility of Researchers/Access to Large Scale Facilities - Research and Technological Development.

Project summary

The Post Correlator Integrator (PCInt) project consist of the design and implementation of an extension to the EVN MkIV data processor to allow higher data output rates. Currently, the output datarate is limited by the 10Mbit/s ethernet cards on the HPUX-RealTime systems found in each correlator rack. The full correlator can be read out 64 times per second. The realtime systems can definitely not cope with this datarate. The realtime systems read the data off the correlator boards via the VME bus.

The correlator board features, apart from the 32 custom VLSI chips, two COTS Texas Intstruments C4x Digital Signal Processors. One of these DSPs is used to calculate the headers that are fed back into the correlator chips, the other DSP is responsible for integrating the data (amongst others). The TI C4x DSP features a high speed serial link. The second DSP's high speed serial link is connected to the front-panel of the correlator board. In order to sustain higher datarates, the following was suggested. Place extra VME-based modules into the correlator racks, equip them with C4x-compatible high speed serial links. Then the correlator board data can be output over these high speed serial links and optionally (depending on the nature and the capabilities of the VME-based module) be processed, in order to bring down the output datarate. After that, the data can be output from these modules to any medium whose controller can be fitted on the VME-based module.


The following list shows links to more detailed descriptions of the various elements in the design/solution.