JOINT INSTITUTE FOR VLBI IN EUROPE

DOCUMENT NUMBER:

PROJECT:	RTD ERB4062PL975013

ISSUE:	DRAFT

DATE:	990302

DESIGN SPECIFICATION

FOR THE

PCI CONTROL BOARD

i.	AMENDMENT RECORD

DATE	ISSUE	DESCRIPTION	PAGES AFFECTED

03-02-99	draft	initial document

ii.	TABLE OF CONTENTS

Ref	Section	Page

i.	AMENDMENT RECORD	2

ii.	TABLE OF CONTENTS	3

1	INTRODUCTION	4

1.1	Purpose of Document	4

1.2	Related Documents	4

2	STATEMENT OF REQUIREMENTS	5

2.1	Role of the PCI control board	5

2.2	General Requirements	5

3	FUNCTIONAL DESCRIPTION	6

3.1	The timing module	6

3.2	The interrupt cycle control module	7

3.2.1	The interrupt cycle counter	7

3.2.2	The interrupt cycle sequencer	7

3.3	VME bus interface	7

3.3.1	Control register access	8

3.4	Implementation	8

3.5	Standard setup sequences	8

3.5.1	EVN setup	8

3.5.2	DZB setup	9

3.5.3	System clock and xclock programming	9

4	HARDWARE DESCRIPTION	10

4.1	Introduction	10

4.2	VMEbus Module	11

4.2.1	VMEbus data transport	12

4.2.2	VMEbus interrupter	15

4.2.3	VMEbus register (0)	16

4.3	Timing Module	16

4.3.1	PLL	17

4.3.2	Clock Distributor	17

4.3.3	Timing Section	19

1	INTRODUCTION

1.1	Purpose of Document

The purpose of this document is to state the requirements for the PCI control board and to review options for meeting these requirements.

1.2	Related Documents

[1]	Design Specifications Post Correlator Integrator - - P. Kamphuis

[2]	Hardware description EVNFRA DZB Correlator Control Board - EVN-doc 56 - P. de Jong, S. Zwier

1.3	Abbreviations

CCC	Correlator Control Computer

DSP	Digital Signal Processing

EMC	Electro-Magnetic Compatibility

LAN	Local Area Network

PCI	Post Correlator Integrator

MB/s	Mega Bytes per second

Mb/s	Mega bits per second

bocf	Begin of correlator frame

TBD	To Be Decided

2	STATEMENT OF REQUIREMENTS

2.1	Role of the PCI control board

The RT system in the PCI is intended to operate similar to the RT system in the correlator. This can be achieved by using the same software for the RT system in the PCI and in the correlator. This software requires some external events (VME interrupts) for proper operation and system synchronization. In the correlator these interrupts are generated by the Control Board [2]. One of the functions of this board is to regenerate the BOCF and the SYSTICK signals for the correlator boards. The control board also generates VME interrupts for the RT system.

It is decided to build a stripped version of the Correlator Control Board. This board will contain all the required logic to present the required events correctly to the RT-system.

2.2	General Requirements

receive SYSTICK signals from correlator rack

regenerated the BOCF locally on board

generate VME interupts on BOCF and SYSTICK

provide interrupt vector on VME interrupt acknowledge

3	FUNCTIONAL DESCRIPTION

3.1	The timing module

The timing module consists of a clockgenerator, a programmable divider, a BOCF pulse generator and a synchronization error detector circuit.

The PLL derives the master clock signal from an externally supplied reference signal REF. (5, 10 or 16 MHz). This clock signal is distributed in the clock distributor to 16 clock buffers with a programmable clock skew that feed the destination via a 50 coaxial connection.

The clock generator circuit covers both the DZB and EVN application by means of a programmable clock generator, that generates the appropriate clock frequencies (32 MHz for EVN and 40 MHz for the DZB mode) from the REF signal.

The master clock signal is applied to the ENSHIFT/RBOCF generator. This is a programmable divider followed by an edge detector for the generation of the ENSHIFT signal for the correlator chips. This signal changes the effective shiftregister clock frequency by a factor n equal to 1,2,4...256. The control board contains 2 independently programmable dividers for each of the correlator segments.

The clock division factors are stored in a VME bus register to be loaded by the VME bus controller.

The ENSHIFT signal can be operated in various modes:

-	In the normal header mode the ENSHIFT signal is unaffected by RBOCF.

-	In the burst header mode ENSHIFT signal is controlled by the RBOCF signal for the corresponding correlator segment. This implements the burst mode for the correlator frame header capture by the correlator chips (see NFRA Note 620, Bos 1994) when RBOCF is high.

-	The oversampling mode is possible only for a division factor n>1. In this case the ENSHIFT signal enables the shift clock in the correlator chips at every n-th sample (in a correlator frame this is sample 0, n, 2n, ......) for the even correlator frames. For the odd correlator frames ENSHIFT is shifted over n/2 master clock cycles. The effect is the correlation of samples

This mode can also be used with the burst header mode.

The programmable divider is synchronized by a system wide synchronization signal SYNC to guarantee phase coherent transfer of data samples.

This signal is supplied by a programmable divider stage that divides the 40 MHz (or 32 MHz) system clock by 40.107 or 32.106 to produce the SYNC signal with a 10 or 1 second period. This divider stage is optionally (under software control) synchronized to an externally supplied SYSTICK signal.

The generator produces also the RBOCF signal to be sent to the correlator segments. The generator is started by the RBOCF SYNC signal supplied by the correlation cycle control module and operates in two modes:

-	In the normal mode the RBOCF pulse width is equal to n times 256 (240) master clock cycles, where n is equal to the clock division factor for ENSHIFT.

-	In burst mode the pulse width is made equal to 256 (240) master clock cycles independent of n.

The period of the RBOCF signal can be chosen independent of the width.

A systick generator circuit is used to keep track of the alignment of the (external) SYSTICK and the internally generated RSYSTICK when the synchronization is disabled. A misalignment event is stored and made available as a status bit to the VME bus controller. A programmable delay of 0,16, 32 or 48 clock cycles in the SYSTICK input is provided to compensate for system wide pathlength differences.

The synchronization of the integration process is done by a COMSYNC signal that is derived from the SYSTICK signal or from one of the EBOCF signals transferred via the serial links. The syncselect circuit takes care of the selection and proper alignment of the COMSYNC 0,1, I signals.

The control bit functions implemented are:

SEL x0-x3	for the selection of the ENSHIFT division factors for the two correlator segments.

ENTICK	to enable the synchronization of SYSTICK by SYNC. If set it enforces the alignment of SYSTICK and SYNC. If not set the SYSTICK generator is free running and the sync error detector indicates a misalignment with SYNC.

SELRSYSTICK	selects the 1 or 10 second period for the SYSTICK signal.

SELxSYNC	there are 3 sets of SELSYNC bits that select the signal to be used for the synchronization of the two correlation cycle control modules (x= 0,1) and the interrupt cycle control modules (x = I). The synchronization signal for the interrupt cycle control module (COMSYNCI) is equal to one of the COMSYNC0+1 signals. Each of the COMSYNC0+1 signals is selected from the EBOCF0+1, EXBOCF and SYSTICK signals.

ENBURST	enables/disables the burst mode for the ENSHIFT signal.

ENOVSAMPL	enables/disables the oversample mode for the ENSHIFT signal.

SELTICKDEL	sets the SYSTICK delay to 0, 16, 32, or 48 clock cycles.

3.2	The interrupt cycle control module

The interrupt cycle control module takes care of the generation of the interrupt signal for the VME bus controller. The interrupt cycle time is normally an integer multiple or an integer fraction of the integration time. It consists of:

a)	a programmable interrupt cycle counter that sets interrupt cycle time equal to NINTERRUPT periods of the CLSYNC clock.

b)	the interrupt cycle sequencer to control the interrupt cycle counter.

3.2.1	The interrupt cycle counter

The interrupt cycle counter is 20-bits long (a copy of the correlation cycle counter). It receives a start signal from the sequencer and returns a ready signal after NINTERRUPT periods of the CLSYNC clock. The possible values for NINTERRUPT are given by:

7 ≤ NINTERRUPT ≤ 2 20 + 2 = 1048578

3.2.2	The interrupt cycle sequencer

The interrupt cycle sequencer controls the interrupt cycle counter. It generates the RBOCFSYNCI signal that is used:

a) to interrupt the VME bus controller,

b) to increment the integration cycle counter.

The interrupt cycle is synchronized to one of COMSYNC signals used by the correlation cycle modules. The synchronization process is enabled by the ENSYNC signal supplied by the integration cycle module. The sequencer operation is controlled by a number of bits set by the VME bus controller (see Appendix A3).

RESETCCI :	resets the control module

DISCOMSYNCI:	disable synchronization with the COMSYNC signal (selects between synchronous and asynchronous mode).

DISENSYNCI:	controls the synchronization enable process in synchronous synchronization mode. If not asserted the synchronization bij COMSYNC is enabled by the ENSYNC signal generated by the integration cycle control module before the start of an integration. If asserted ENSYNC is disabled and COMSYNC is continuously enabled.

3.3	VME bus interface

The control board acts as a slave in the extended address space (A32) of the VME bus. The interface will respond only to:

- long word accesses (D32)

- the address modifier codes 09, 0A, 0D and 0E (hex) for single word transfers.

The 31-bit address is divided into an 8-bit board address that is selected via a DIP switch. The remaining 23 bits are decoded in an EPROM and assigned to 19-bit base address and a 3-bit register address (only long word addresses are accepted with A1=0). The VME bus controller writes the 11 bits of the VME bus register as follows:

- a 3-bit wide field for the enable bits for the 3 interrupt sources,

- a 5-bit field to specify the last five bits of the interrupt vector,

- a 3-bit field to select the interrupt priority on the VME backplane (1 - 7).

The interrupt vector returned to the VME bus controller is 20-bits wide.

The first 3 bits are used to identify the SYSTICK, RBOCF, INTRDY interrupts. Bits 3-13 are equal to the 11-bits interrupt vector stored in the VME bus register. The bits 14-19 contain the board identification code.

The bit assignment for the VME bus register can be found in Appendix A4.

The VME bus interrupts are handled by a VME bus driver described in EVNFRA Note 644 (EVN Doc 72).

3.3.1	Control register access

The control board has 8 control registers that can be accessed from the VME bus. The control register addresses are assigned contiguously with an address base determined by the upper 8 address bits set by the on-board DIP switch.

The registers can be directly accessed using vme_phys_write and vme_phys_read system calls with the DATA_ACCESS + A32 address modifier values or via the system wide shared memory address mapping. The latter maps the VME bus address space into the user process address space.

3.4	Implementation

A detailed hardware description can be found in NFRA note 630 (EVN doc 56).

The logic makes use of FPGA's that need to be programmed in the start up phase of the board. Provisions have been made to automatically load the required information from an on-board ROM during power up. In addition it is possible to load from the on-board ROM under computer control. For test purposes a possibility has been added to download the programming information via the VME bus. The VME bus register control bits involved are summarized in Appendix A.4.

The control board is a 6U x 160mm sized board. That the input and output signal specification is summarized in Appendix A.1. The board contains 2 backplane connectors. P1 and P2 are standard VME bus connectors.

3.5	Standard setup sequences

The setup of the control board covers a large number of different possibilities.

A standard setup should follow the following steps:

a)	Program the system clock and xclock chips with the desired frequency.

b)	Disable hardware interrupts (clear register 0).

c)	Set all registers to the required value with, for register 3, the reset bits of the CCCM0, CCM1, INCM and ICCM modules set in addition to its required value.

d)	Clear the reset bits set in step c.

The reset operation is required for a properly synchronized startup of the control modules.

3.5.1	EVN setup

The EVN system uses a 32 MHz system clock that produces a 1 second or 10 second SYSTICK signal. A 40 MHz (DZB) clock will then produce a 0.8 or a 8 second SYSTICK.

It is assumed that all BOCF's are identical. The BOCF period should obey the relation:

NINTCYCLE x NCORRCYCLE = 106

where

NCORRCYCLE	is the number of CLSYNC cycles of the BOCF's generated by the CCCM 0, 1 and INCM.

NINTCYCLE	is the number of IBOCF cycles of the ICCM.

A setup for the synchronous and continuous mode should use the following control word settings.

Register	Value	Comment

0	0x1c00	BOCF + SYSTICK interrupt on.

0	interrupts off.

1	0

2	0x4188	SYSTICK = 1 sec; ENSHIFT = 32 MHz.

3	0x69C0C0	Synchronous + continuous + resets on.

0x2800C0	Synchronous + continuous + resets off.

4	65537 - NINTCYCLE

5	1048578 - NCORRCYCLE	no blanking.

6	equal to 5

7	equal to 5

3.5.2	DZB setup

The DZB uses a 40 MHz system clock to produce a 10 second or 1 second SYSTICK.

Use of a 32 MHz clock implies that the SYSTICK will be equal to 12.5 or 1.25 seconds.

When all the BOCF periods are identical they should obey the relation:

NINTCYCLE x NCORRCYCLE = 16,000,000

where:

NCORRCYCLE	is the number of CLSYNC cycles of the BOCF signals generated by the CCCM 0,1 and INCM.

NINTCYCLE	is the number of IBOCF.

A setup for the synchronous and continuous integration with default values for NCORRCYCLE and NINTCYCLE should use the following control word settings:

Register	Value	Comment

0	0x1c00	BOCF + SYSTICK interrupts on

0	interrupts off.

1	0

2	0x0188	SYSTICK = 10 sec; ENSHIFT = 40 MHz.

3	0x69C0C0	Synchronous + continuous + resets on.

0x2800C0	Synchronous + continuous + resets off.

4	65537 - NINTCYCLE

5	1048578 - NCORRCYCLE	no blanking

6	equal to 5

7	equal to 5

3.5.3	System clock and xclock programming

There are two phase locked oscillators on the control board that need to be programmed prior to using the board. The SYSCLOCK oscillator is used to generate the 32 or 40 MHz system clock. The xclock circuit is used as a synchronization signal for the serial link that receives the external SYSTICK and REF clock from an external source.

The programming sequence for the setup of the two pll's should follow the sequence described in the documentation of the CGS140 circuit used.

The setup sequence is similar to the one described in MkIV memo 227. It has been implemented in software in the RDWRHY_cgs140 routine kept in the evnfra_rwhx.c file.

4	HARDWARE DESCRIPTION

4.1	Introduction

This document describes hardware of the EVNFRA Control Board. A block diagram of the control board is shown in figure 1.1.

The control board contains two main functions. They have very little to do with each other. They only shares the VMEbus module.

One main function involves the generation of:

-	the local BOCF signal for the subsystem;

-	time reference signals to the crate controller;

-	various support signals concerning the correlation process on the correlator boards.

The modules responsible for this are the Unit Sync Module, Timing Module and Control Module.

The other main functionality is the monitoring and a certain level of protecting the modules in a crate. This involves:

-	monitoring of the output voltage of the various power supply modules in a crate;

-	monitoring the temperature in a crate and when the temperature rises too high it switches
off the power supplies.

The Monitoring Module is responsible for this.

4.2	VMEbus Module

The VMEbus interface performs the interfacing tasks between the VMEbus and the local circuits on the board. The VMEbus interface can only act as a Slave interface. It responds only to 32 bits addressing modes (A32) and is capable of handling data transfers of 32 bits wide (D32). The VMEbus interface can also act as an interrupter. There are 3 inputs available for local circuits for doing interrupts. The required interrupt vector is supplied by the interface. The interrupt vector consists of 3 bits telling which interrupt source has made the interrupt and a 5 bits unique word that tells from which board in the system the interrupt is coming from.

The VMEbus interface is built up around a XILINX EPLD XC73108-15PC84. Almost the whole VMEbus interface fits in one big EPLD. We have chosen to do the board address and base address decoding outside the EPLD, so we could choose a smaller and cheaper plastic package.

4.2.1	VMEbus data transport

The data transport section of the VMEbus interface is illustrated in figure 2.2. The circuit is capable of handling single 32 bits data transfers. It does all the necessary handshaking with the VMEbus. The local circuits must take care of there own registers. The VMEbus interface provides control signals, so that make this an easy task. The databus is buffered by the interface.

A module is selected with a high level on SELECT. The global signal DDIR determines the direction of the data transfer. During a VMEbus write cycle is the DDIR signal low. The databus drivers must enable their outputs when DEN is low. Naturally only the selected modules may access the local data bus. The modules must latch the data on the local databus on the positive going edge of DLOAD.

Figure 2.2 is a schematic representation of the equation based design of the VMEbus interface. The VMEbus interface is fully written in the ABEL language. The ABEL source code is enclosed. The signal names in the figure corresponds with the pin and node names used in the ABEL source.

The board address decoder compares the VMEbus address line's A[31:24] with the 8 bits board address from the DIP switch. The base address decoder compares address line's A[23:5] with the 19-bits base address of the DIP switch. When these two are equal AMATCH0 and AMATCH1 will be high.

The A32 cycle decoder checks if the VMEbus cycle is not an interrupt acknowledge cycle and if the address modifier corresponds to the access modes allowed. When this is the case, EXAMMATCH will be asserted.

The D32 cycle decoder makes D32CYCLE high when it is a long word data transfer. When all above these conditions are met, the board is correctly addressed and BOARDSEL will be high.

The register select decoder decodes address line's A[4:2] to eight register select lines SELECT[7:0]. The decoded output becomes active at the positive going edge of SYNCCYC, when BOARDSEL is true. The synchronized VMEbus cycle signal SYNCCYC is delayed sufficiently long by the D-FF to make sure BOARDSEL is stable.

The data output enable signal DEN becomes true one the positive going edge of SYNCCYC.

DLOAD becomes true during a VMEbus write cycle at the positive going edge of DSYNCCYC. The signal DSYNCCYC is an SYNCCYC signal delayed one SYSCLK clock period. This gives the selection logic time to settle, the data to propagate trough buffers and to comply with a setup time before the arrival of DLOAD.

DTACK becomes true when external circuits acknowledge their data with a positive transition of DTACKIN0 or 1. The VMEbus interface generates the DTACK for registers that don't have acknowledge logic. This is the case for the registers 0 and 1. The DTACK becomes true at the positive transition of DSYNCSYC.

Normally the registers latch their data at the negative edge of the DLOAD signal and DLOAD is negated at the end of the VMEbus cycle. This will not work when configuration data to the XILINX FPGA is written. The FPGA in aynchronous peripheral mode expects a write strobe pulse of an minimum length of 100 ns. Therfore the DLOAD signal is negated at the DDDSYNCCYC signal. This gives a DLOAD pulse of 125 ns length.

All control signals stay stable until the DS signals are negated. This makes address pipelining possible.

The description of the VMEbus interface is illustrated with timing diagrams. The timing diagrams are created with board level timing simulations. The signals are measured at board level.

In Fig. 2.3 a VMEbus write and read cycle to register 2 is shown. The simulations are done with a 20 MHz SYSCLK instead of the specified 16 MHz. This is done because that makes the definition of the SYSCLK signal in the simulator easier and the simulation for the circuit harder. On t=4.1 us all the necessary VMEbus input signals for a write cycle are made active. The AS and DS0,1 signals are also without any delay activated. This is a very fast access, in reality there can be a more relaxed timing expected. The circuit responds with asserting the signals: DDIR, DEN, SELECT2 and DLOAD. When the external register is selected (before DLOAD is asserted), it acknowledges the data by asserting DTACKIN0. The VMEbus interface generates a DTACK. After the DTACK is asserted, the VMEbus cycle can be terminated.

At t=4.35 us a VMEbus read cycle is started.

4.2.2	VMEbus interrupter

The interrupter section of the VMEbus interface module is shown in figure 2.4. This is a schematic representation of the equation based design of the VMEbus interface module. The signal names do correspond with the pin and node names in the ABEL source code.

The VMEbus control register is not shown in this picture. The circuit can only act as an interrupt requester.

The circuit has three interrupt inputs INT[2:0] available for local circuits. These three interrupt inputs can generate one interrupt request IRQ on the VMEbus. The IRQ level is programmable to all seven IRQ levels with the control bits IRQSEL[2:0]. The three interrupt inputs can be separately disabled and enabled with the control bits ENINT[2:0]. The circuit responds only to a 32 bit interrupt acknowledge cycle (D32) and returns a 20 bit STATUS/ID on D00-D31.

A positive going edge of an interrupt INT input will latch the event. When one positive going edge is detected then one IRQ output becomes active. The IRQ level depends of the IRQSEL bits in the control register. The interrupt handler has to respond with an interrupt acknowledge cycle. When it is a 32 bit interrupt acknowledge cycle, D32ACK will be high and when the three bits code on A[3:1] corresponds to the IRQ generated then OURIACKCYCLE will be true. On the positive going edge of SYNCIACKCYC, IACKOUT stay low and the IACK daisy-chain will not pas on. On the same positive going edge of SYNCIACKCYC, IRQREGEN is asserted and the STATUS/ID will be put on the data lines. After an other SYSCLK, when the data is stable, DTACK will be asserted on the positive going edge of DSYNCIACKCYC.

The IRQ is released by the DTACK during the interrupt acknowledge cycle. This is called an ROAK release mechanism.

During an interrupt acknowledge cycle not conform our IRQ level or when there is no IRQ at all, OURIACKCYCLE will be low. In this case an active level on IACKIN will, after a short delay, be passed through to IACKOUT.

To prevent that the decision to take part at the Daisy-chain is changed during an interrupt acknowledge cycle the status of IRQX is sampled at the start of the cycle. This prevents the stealing of the IACK cycle, meant for an other interrupter.

DTACK and IACKOUT are released under different circumstances. IACKOUT must be negated within 30 ns after AS is negated and DTACK should only be negated when the handler negates DS0 to allow address pipelining.

4.2.3	VMEbus register (0)

The VMEbus interface EPLD XILINX XC73108-15 contains a 20 bit register. This register can be read and/or written by a normal data access. The VMEbus register listens to register address 0. This register is also returned as interrupt vector as part of the interrupt acknowledge cycle. The bit assignment in this register are:

0-2	IRQSOURCE	The 3 interrupt inputs; bit 0 is the regenerated BOCF signal of the interrupt cycle control module (INCM) (RBOCFSYNCI), bit 1 is the regenerated SYSTICK (RSYSTICK) and bit 2 is the integration ready signal of the integration cycle control module (ICCM). A positive edge of the input signal will set the corresponding bit. When the VMEbus interrupts are enabled, IRQSEL has another value then 0, then the bits are cleared after the interupt acknowledge cycle. A VMEbus read do not effect those bits. When, at the other hand, the VMEbus interrupts are disabled, IRQSEL = 0, then the bits are cleared after a VMEbus read.

3-7	IVECTOR	The interrupt base vector. The 5 bits of the interrupt base vector are programmable by the VMEbus. With the 3 IRQSOURCE bits this bits form an interrupt vector.

8-10	IRQSEL	The interrupt level select bits. The 3 bits determines the level of the VMEbus interrupt, IRQnr. = IRQSEL0-2. The VMEbus interrupts are disabled with interrupt level 0.

11,12,13	IBOCF, ISYSTICK and IINTRDY

The interrupt enable bits of the interrupt inputs. The VMEbus interrupt are, for the 3 interrupt inputs separately, to enable. The status of the disabled inputs can still be read from the register. How the reset of the inputs takes place still depends of the IRQSEL setting.

14-19	IDENT0-5	The VMEbus interface has 6 available input lines that can be read from the VMEbus register. These lines are used for a unique identification code of the control board.

4.3	Timing Module

The timing module is responsible for the generation of the clocks required for the sub system and various parts of the control board. A block diagram of the timing module is given in figure 4.1.

4.3.1	PLL

The PLL transforms the 5/10 MHz reference clock signal CLREF from the serial link module to the 32/40 MHz system CLOCK frequency. The circuit is capable of generating 32 or 40 MHz out of both 5 or 10 MHz.

The PLL is built up around the PLL IC VM305, who has all the necessary divider stages on board to convert directly the 5 or 10 MHz to 40 MHz. For generation of the 32 MHz signal system clock out of the 5 or 10 MHz signal the PLL is proceeded by an external divide by 5 divider stage. The selections are made by the following jumper settings:

CLREF	CLOCK	J28	J29	J30

5 MHz	32 MHz	1-2	1-2	1-2

10 MHz	32 MHz	2-3	1-2	1-2

5 MHz	40 MHz	1-2	2-3	2-3

10 MHz	40 MHz	2-3	2-3	2-3

4.3.2	Clock Distributor

The Clock Distributor does the distribution of the 32/40 MHz system clock. All boards in the subsystem and the local modules on the control board are connected to a separate clock buffer. The Cypress CY7B992 is used as clock buffer. All clock lines are terminated by means of series terminations of 50 ohms. All clock signals can individually shift a few ns in phase to eliminate errors introduced by differences in length of the connections. The adjustment is done by means of jumper settings. More information about this can be found in the Cypress CY7B992 documentation.

4.3.3	Timing Section

The timing section is responsible for generating the basic clocks for the sub system and for the control board itself. The timing section is fully implemented in an XILINX 4003PC84-5 FPGA. The signals are derived from the 32/40 MHz system clock (CLOCK) and can be synchronised by the 1/10s synchronisation signal (SYSTICK).

Fig. 4.3 shows the block diagram of the timing section. It contains for each of the correlator segments a clock divider and an ENSHIFT/RBOCF generator with common support circuitry. The 20 bit control register is not shown in the figure.

The output signals that leave the PCB are synchronised by an additional buffer. These buffers are not shown in the figure. These buffers are located close to the connector.

The subsystems are synchronised with each other by the SYSTICK synchronisation signal. This signal is distributed over all the subsystems by means of a serial link. This signal is received by the serial link receiver and supplied to the timing section.

4.3.3.1	The SYSTICK DELAY

The block SYSTICK DELAY introduces a programmable delay in the SYSTICK signal. This delay compensates the delays introduced by the transmission of the data between the subsystems. A subsystem further on in the data stream receives its data later then one at the beginning of the stream. This additional delay can be set with the two jumpers SELDELAY0, 1 respectively jumper J4 and J5. The following delay settings in units of CLOCK periods can be made:

J4	J5	(additional)delay

0	0	0

1	0	16

0	1	32

1	1	48

4.3.3.2	The SYSTICK REGENERATOR

The Delayed SYSTICK is connected to the block SYSTICK REGENERATOR. The SYSTICK REGENERATOR is a free running so called flywheel circuit. The circuit can generate his own Regenerated SYSTICK signal without any input signal. The circuit synchronises on the DSYSTICK signal if ENTICK is true. When synchronisation has been established, the SYSTICK signal can be removed and/or ENTICK can be negated without disturbing correct operation.

With SELRSYSTICK can be selected between a 1 and 10s period of RSYSTICK.

The circuit compares also his input signal DSYSTICK with his generated signal RSYSTICK. When they not arrive simultaneously, for example when the circuit is synchronising (that takes a few SYSTICK's) or there is something wrong with SYSTICK, a synchronisation error (TICKERR) will be generated. This (pulse) signal is latched by the control register, so the event is stored. The event is cleared after a read of the control register. The TICKERR signal is also connected to an LED on the frontpanel.

4.3.3.3	The SYNC SELECT

With the block SYNC SELECT can be chozen between the signals RSYSTICK, EBOCF0 or EBOCF1 for synchronisition purposes. In normal operation synchronisation is done by the RSYSTICK signal. For testing purposes it is possible to synchronise on the EBOCF0/1 signal, supplied by respectivily the input board of segment 0 and segment 1. The selection is done by the two bits SEL0SYNC for segment 0 and SEL1SYNC for segment 1. Synchronisation of an segment involves the logic in the timing unit for that segment and the correlation cycle control module (CCCM) in the control modul for that particular segment. The following selections can be made:

SEL0(1)SYNC	Synchronisation source

0	RSYSTICK

1	EBOCF0

2	RSYSTICK

3	EBOCF1

4.3.3.4	The COMSYNC SELECT

With the block COMSYNC SELECT the synchronisation signal COMSYNCI and the corresponding driving clock signal CLSYNCI for the interrupt cycle control module (INCM) in the control module can be selected. This selection determines if the interrupt cycle controller runs synchronously with segment 0 (SELISYNC=0) or segment 1 (SELISYNC=1).

4.3.3.5	The CLOCK DIVIDER

An important part of the timing section is the CLOCK DIVIDER. This block is responsible for generating the several clock frequencies needed by the system. The clock dividers divide the 32/40 MHz system clock (CLOCK) down to a number of different frequencies. The CLTEST signal is used by the input boards for testing purposes. The CLTEST signal has a fixed frequency of CLOCK/64. The CLSYNC signal is used as driving clock for the control module. The CLSYNC signal has a fixed frequency of CLOCK/32. The ENSHIFT signal is used as enable signal of the shift registers in the correlator chips. The ENSHIFT signal needs to be set at a number of frequencies. The frequency is dependent of the factor of over sampling of the input data. The frequency of ENSHIFT is determined by CLENSHIFT signal. The frequency of the CLENSHIFT signal can be programmed at 8 different frequencies by 3 bits SEL[2:0] in the control register.

CLENSHIFT = CLOCK/2(SEL[2:0]+1)

The output signals of the CLOCK DIVIDER are synchronised by the COMSYNC synchronisation signal.

4.3.3.6	The ENSHIFT/RBOCF GENERATOR

The ENSHIFT/RBOCF GENERATOR generates the ENSHIFT and RBOCF signal. This block shapes the CLENSHIFT signal supplied by the CLOCK DIVIDER to the ENSHIFT signal. The ENSHIFT signal has the same frequency as the CLENSHIFT signal but has a fixed high time of one CLOCK period. If bit SEL3 in the control register is set to 1 the ENSHIFT frequency is not determined by the CLENSHIFT signal anymore, but is set at constant high level. In normal operation the ENSHIFT signal starts with the high period at the start of the BOCF cycle. In oversample mode (ENOVSAMPLE=1) the ENSHIFT signal is shifted over a half of its own period every odd BOCF cycle. The first BOCF cycle at the start of an integration is called BOCF cycle 0.

The COMSYNC signal is used to set the toggle mechanisme at the even BOCF period. In synchronous operation of the control module works this well because an integration starts always at the COMSYNC signal.

This block also generates the active (high) period of the RBOCF signal. The RBOCF timer is triggered by the RBOCFSYNC signal from the control module. Note that only the high time of the RBOCF signal is determined by the RBOCF timer not the period time. The period time is determined by the RBOCFSYNC signal from the control module. In normal operation the high time of the RBOCF signal is dependent of the ENSHIFT frequency. The minimum high time of the BOCF signal is equal to 256/240 (DZB/EVN) CLOCK periods and will be multiplied by the same oversample factor as the ENSHIFT signal. In burst mode (ENBURST=1) it is like no oversample factor is used during the BOCF high time. The high time of the RBOCF signal is then equal to 256/240 CLOCK periods and ENSHIFT is forced high.

In the example below (fig. 4.4) the RBOCF and ENSHIFT signal is shown. In this example the minimum high time of RBOCF pulse is made equal to 4 CLOCK periods. This not a realistic value but it makes the example more clearly. The ENSHIFT signal has a frequency (four times oversampled data) of CLOCK/4 (SEL[3:0] = 1).

In the figure is shown what happens in oversample mode (ENOVSAMPLE=1). In oversample mode the ENSHIFT signal is shifted over a half period of the ENSHIFT signal every odd RBOCF cycle. Also is shown what happens to the RBOCF signal and ENSHIFT signal in burst mode (ENBURST=1). In burst mode the RBOCF signal is always 4 CLOCK periods (in this example) long, independent of the frequency of ENSHIFT.

4.3.5.1	The RBOCF/ENSHIFT GENERATOR realisation

The realisation of the RBOCF/ENSHIFT GENERATOR can be found in drawing 14058. In the schematic can been seen that several shift registers are used to realise a correct alignment of the signals with each other. It is important to know which path in the circuit must be as fast as possible and which paths needs additional delays in order to make it work. The timing and control module are synchronous designs. The delays mentioned above are introduced by shift registers clocked by the CLOCK signal. The timing of the timing and control module is determined by the path of the RBOCF signal. The RBOCFSYNC signal generated by the control module must arrive as soon as possible. The control module is in its turn dependent of the COMSYNC signal. The timing unit is in its turn responsible for the COMSYNC signal. The COMSYNC signal connected to the RBOCF/ENSHIFT GENERATOR is not the same COMSYNC signal that is connected to the control module. This signal is slaved to the RBOCFSYNC signal and has an additional delay. The COMSYNC and the RBOCFSYNC signal arrive at the same time at the Toggle flip-flop of the RBOCF/ENSHIFT GENERATOR. This is only at the start of an integration but this situation determines the timing of the COMSYNC signal. The output of the T-FF is inverted every RBOCFSYNC period and is reset when COMSYNC is active. The critical path runs further from the T-FF to the XOR gate. A high level at the output of the T-FF does invert the CLENSHIFT signal, at every odd RBOCF periods in the oversample mode. This results after the pulse shaper in an over a half period shifted ENSHIFT signal. The positive edge of the CLENSHIFT signal must be aligned to the output signal of the T-FF. This CLENSHIFT signal is also connected with a pulse shaper and FF to the clock enable (CE) input of the RBOCF timer. The pulse shaper transforms the CLENSHIFT signal to a signal with a high time of one CLOCK period at every rising edge of the CLENSHIFT signal. The FF is introduced to satisfy the setup time of the CE input of the RBOCF timer. This signal decides the timing requirements of the RBOCFSYNC signal connected to the RBOCF timer. The START and count enable signal must arrive at the same time to preset the synchronous RBOCF timer. The ENSHIFT signal (the signal from the pulse shaper at the top side of the drawing) must align to the output of the RBOCF timer. This has to do with the burst mode. The last shift register in the output of the ENSHIFT signal is to comply the external timing requirements.