JOINT INSTITUTE FOR VLBI IN EUROPE

DOCUMENT NUMBER:

PROJECT:	RTD ERB4062PL975013

ISSUE:	DRAFT

DATE:	990121

DESIGN SPECIFICATION

FOR THE

POST CORRELATOR INTEGRATOR

i.	AMENDMENT RECORD

DATE	ISSUE	DESCRIPTION	PAGES AFFECTED

11-24-98	draft	proposed PCInt prototype	9-11, 13-14,18-21

01-21-99	draft	revised document

ii.	TABLE OF CONTENTS

Ref	Section	Page

i.	AMENDMENT RECORD	2

ii.	TABLE OF CONTENTS	3

1	INTRODUCTION	5

1.1	Purpose of Document	5

1.2	Related Documents	5

1.3	Standards	5

1.3.1	JIVE Standards	5

1.3.2	National Standards	5

1.4	Abbreviations	5

2	STATEMENT OF REQUIREMENTS	6

2.1	Role of PCI	6

2.2	Applications	6

2.3	General Requirements	7

2.4	Proposed PCI Architecture	11

2.5	Synchronization	12

2.6	Hardware Interfaces	13

2.6.1	PCI Inputs	13

2.6.2	PCI Outputs	13

2.6.3	Control Interfaces	13

2.6.4	Synchronization Interfaces	13

2.7	Installation Requirements	13

2.8	Electrical Requirements	14

2.9	EMC Requirements	14

2.9.1	Emissions	14

2.9.2	Susceptibility	14

2.10	Safety Requirements	14

2.11	Environmental Requirements	14

3	INITIAL HARDWARE DEFINITION	15

3.1	Hardware selection	15

3.1.1	Processing board	15

3.1.2	Recording board	16

3.1.3	Control module	17

3.2	Construction	18

3.2.1	Physical	18

3.2.2	Internal Interconnections	18

3.2.3	External Interconnections	18

3.2.4	Connector types.	18

3.3	Supply Rails	19

3.3.1	Allocation	19

3.3.2	Additional Supplies	19

3.4	Power budgets	20

3.5	Power Supply and signal transmission/grounding	20

3.6	Cooling	20

3.7	Control Computer	20

3.8	DSP Module	20

4	PROJECT DOCUMENTATION AND CONTROL	21

4.1	Documentation	21

4.1.1	Media	21

4.2	Change Control	21

4.2.1	Hardware/Firmware	21

4.2.2	Software	21

5	TESTING	22

5.1	Test Philosophy	22

5.2	Test methods	22

5.3	Test equipment	22

5.4	Test plan	22

A.	ORDERING INFORMATION	23

Hardware	23

Development Software	25

B.	PMC - The New Super Mezzanine Standard	26

What is PCI	26

Mezzanine Problems ... and Solutions	26

The PMC Standard	26

Benefits	27

1	INTRODUCTION

1.1	Purpose of Document

The purpose of this document is to provide an equipment specification for the Post Correlator Integrator (PCI) This document also defines the methods, standards and procedures to be adopted in the design, development, manufacture and testing of the PCI.

1.2	Related Documents

Actual Cost Contract No. FMGE-CT98-0101 (DG12 MEMO)

{anything else?}

1.3	Standards

1.3.1	JIVE Standards

{do we have any?}

1.3.2	National Standards

Electronic Industries Association (EIA) RS-232-C Interface Between Data Terminal Equipment and Data Communication Equipment Employing Serial Binary Data Interchange.

European standard EN 60 950 Safety of information technology equipment including electrical business equipment.

Electromagnetic Compatibility, Council Directive 89/366/EEC.

{do these apply? Are there any more?}

1.4	Abbreviations

CCC	Correlator Control Computer

DSP	Digital Signal Processing

EMC	Electro-Magnetic Compatibility

LAN	Local Area Network

PCI	Post Correlator Integrator

MB/s	Mega Bytes per second

Mb/s	Mega bits per second

TBD	To Be Decided

2	STATEMENT OF REQUIREMENTS

2.1	Role of PCI

The PCI enhances the capability of the EVN/JIVE Correlator by providing an output path for data rates that exceed the maximum transfer rate of the LAN. To achieve this the PCI receives outputs from the correlator and performs various re-ordering and DSP functions. In general these processes will result in a reduction in the volume of data to be passed to an output port and/or data storage device.

2.2	Applications

In order to come to a specification to the Post Correlator Integrator it is necessary to identify the possible applications for the PCI.

General application

The most general application is to allow the maximum data rate of the C40 communication ports (roughly up to 10 MB/s for each correlator board) of the correlator boards. Resulting in an aggregate input data rate of 320 MB/s. It should be possible for the user to select processing and data handling functions to be performed on the received data. Finally it must be possible to store the processed data on a storage device for further analysis.

The data rate to the storage device depends on the results of the processing function, so it is even possible that no actual data reduction is achieved. This results in a output data rate of the PCI of approximately 320 MB/s.

Pulsar Search Mode Application

A specific applications for the PCI is in a Pulsar Search Mode Application. This application requires high speed read out of the correlator boards. This data read out should be as fast as possible and could go up to reach 102.5 times per second for the DZB and 64 times per second for the JIVE correlator. Every time the full contents of all correlator boards is read (20 Kword). With 32 correlator boards (8 boards per rack, 4 racks) data will be dumped out with an aggregated data rate of 1280 - 2051 Mb/s. This data rate is received via 32 C40 communication ports, with a data rate of 40 - 64.1 Mb/s each, i.e. about 5 - 8.1 MB/s.

For 16 stations with 16 channels (subbands) per station there are 16 auto correlations and 120 cross correlations per channel. So there are only 2176 independent correlation products each of which can be reduced to 8 - 32 complex spectral bins, resulting in about 17 MB/s output data rate.

The pulsar search application is an observation of maximally 12 hours.

Multiple field centre processing

The multiple field centre processing application only applies to the JIVE correlator (note: the JIVE correlator produces complex correlation products). In multiple field centre processing the correlator is used with the shortest possible integration time. The fringes are multiplied by the PCI using a complex multiplication to move the field centre to a different location. After the multiplication the data is accumulated for a period and finally Fourier transformed. It is possible to multiply the correlator data with different coefficients to produce sets of data with different field centres. A maximum of 16 field centres is expected.

The output data rate for this application is determined by the following parameters, integration time (count) and the number of field centres to process.

The correlator data received from each correlator board is 20 Kword per 9.75 msec, i.e. about 8 MB/s.

Output rate = 8 Mbyte *number of centres / integration count

i.e. with 16 field centres and 1 second integration, 1.3 MB/s

This data rate is for one correlator board, there are 32 correlator boards in the correlator resulting in an aggregated data rate of 40 Mbyte / sec.

Recirculation

The correlator has the capacity to calculate all the correlations between 16 antennas (stations) in all 4 polarizations for a total bandwidth of 160 (128) MHz. For smaller bandwidth and/or less polarizations and or a smaller number of antennas, the correlator has an overcapacity that can be used to increase spectral resolution.

For recirculation the input signal bandwidth is a factor r (recirculation factor) smaller than the correlator bandwidth. The incoming data samples are stored in a double buffered recirculation memory. Because the correlator bandwidth is r times higher, the second buffer can be read r times while the first buffer is filled. So the same input data can be processed r times by the correlator with different configurations each time. This can result in an amount of correlator output data that is r times larger than without recirculation.

Processing functionality

The PCI must be able to receive data from the correlator through 32 C40 communication ports with the maximum possible C40 communication port data rate of about 10 MB/s, however the correlator data output is in chunks of much higher burst transfer rates of up to maximal 20 MB/s.

In all possible applications, it must be possible to perform several operations on the received data. It must be possible to select a set of correlator products from the data (data reduction) and perform several calculations, i.e. complex multiplication, Fourier transform or accumulation, on the selected correlator products. All the calculations are correlation function based, i.e. their input is one correlator function.

The correlator data processed by the PCI must be stored on a storage device by the PCI. The PCI output rate depends on the input data rate and the amount of data reduction achieved by the processing

The different processing functions to be performed are defined and controlled by the operator on the CCC. For the CCC it must be possible to configure the PCI and to monitor the status of the PCI.

It might be useful to be able to access the stored data for off-line processing even if the used medium is removable. Without any additional costs it would then be possible to check, process and transfer the data to another storage device.

2.3	General Requirements

From the possible applications for the PCI the following requirements can be extracted:

1	The PCI must fit within the correlator design

2	Receive control messages from the Correlator Control Computer (CCC)

3	Interpret control messages to determine which of a defined set of processes is to be performed.

4	Receive multiple channels of correlator data

5	Store and re-order the data as required

6	Accumulate data as required

7	Perform DSP algorithms such as complex multiplication and Fourier transformation as required.

8	Report status information to the CCC on request.

9	Pass the product of processing to TBD output port or removable storage media.

10	The storage media must have a large capacity to store several hours of observations.

Fit within the correlator design

The PCI must integrate within the correlator design when possible. This means it has to fit within the correlator crates when possible. Preferably it should reside in a VME rack with the same RT-system as the correlator using the same software. In this way the PCI can be a transparent extension to the correlator. It will just add an additional place for processing the data with some additional capabilities and an additional output path for the correlated data.

Receive control messages from CCC

The communication between with the CCC is performed via the RT system. The connection between the CCC and the RT system is a Ethernet connection. The communication between the RT system and the PCI processing components is always a master-slave communication, with the RT system acting as a master.

Interpret control messages

Interpreting control messages from the CCC is basically a software processing task. However if the control messages are received by the System Controller in a VME system, a communication path with the DSP-boards must be available.

Receive multiple channels of correlator data

A correlator board produces 16 Kword (64 Kbyte) of lag data and 4 Kword (16 Kbyte) of header and status information every 9.75 msec. This data is consists of maximal 256 correlator products. The correlator lag data is complex for the EVN-JIVE correlator and real for the WSRT application. There must be at least 20 Kword (80 Kbyte) of free memory every 9.75 msec for each correlator board connected to the PCI.

The received correlator functions must be random accessible for further processing. Only the required correlator functions should be processed by the PCI.

Store and Reorder data

Incoming data received from the correlator must be stored in memory buffers for further processing by the PCI. If one PCI subsystem handles one correlator segment, it should also be possible to reorder or combine correlation products from different correlator boards within that correlator segment. It must also be possible to process only the required correlation products, so a selection has to be made which products to process.

Accumulate data

Data accumulation can be performed at different stages in the processing path, i.e. after each processing step. Theoretically accumulation of the input data can also be performed although in that situation the correlator could perform the accumulation as well.

In normal operation there must be 16 Kwords (64 Kbytes) of memory available to store and accumulate the data coming from one correlator board. This amount of storage space can go up to 16 times 16 Kwords in case of maximum recirculation. So for data accumulation at least 1 Mbyte of memory is required for each correlator board to process. Depending on which additional information coming from the correlator is to be stored another 16 x 16 Kbytes = 256 Kbytes of memory is needed.

Processing functionality

After the reordering and selection stage there are one or more processing functions possible; complex multiplication, accumulation and / or Fourier transformation {anything else?}. All these processing operations should be defined as separate tasks and could be executed in any possible order to achieve the required processing of the correlator data. The processing power requirement largely depend on the order of execution of these processing functions.

There are several benchmarks available, most of them are based on the original TI implementations. These figures can be used to identify and verify the available processing power.

The correlator produces 16 Kwords of correlation products every 9.75 msec. This can contain complex and real correlation products with lags ranging from 64 (32 complex) to 16384 (8096 complex). The most processing power is needed for Fourier transformation of these correlation products. These transformations must be performed with in 9.75 msec interval, allowing other processing to be performed as well. The following tables show the available time for the Fourier transformation.

Complex Fast Fourier Transform (integration interval 15.625 msec)

products	lags	allowed time
256	32	61 usec
128	64	122 usec
64	128	244.1 usec
32	256	488.2 usec
16	512	976.5 usec
8	1024	1953.1 usec
4	2048	3906.2 usec

Real Fast Fourier Transform (integration interval 9.75 msec)

products	lags	allowed time
256	64	38 usec
128	128	76.1 usec
64	256	152.3 usec
32	512	304.6 usec
16	1024	609.3 usec
8	2048	1218.7 usec
4	4096	2437.5 usec

Report status information to CCC

The required status information has to be determined.

Removable storage media

The constraints on the PCI output largely define the architecture of the PCI. The storage device used for the PCI should be a removable device. In general removable devices have a slower access time than non-removable devices, but with a larger storage capacity.

An Internet search revealed several options for fast data storage to removable devices. The most common is DAT-tapes with a restricted capacity of 24 GB per tape and a data transfer of 2.4 MB/s (compressed). A tape system used for more demanding applications is the DLT-tape. With a slightly larger capacity and transfer rate than DAT-tape. (Quantum DLT 7000; 10 MB/s and 70 GB compressed). For the most demanding applications the AMPEX DST tape system can be used. AMPEX DST tape systems offer the best performance with storage capacities of 50 GB, 150 GB and 330 GB per tape and a sustained transfer rate of 15 MB/s.

Media	transfer rate (MB/s)	capacity (GB)

DAT (DDS3)	2.4	24

DLT	10	70

DST*	15	330

* without data compression

In order to increase the performance of the storage media it is possible to use an array of drives. There are several arrays (or libraries) on the market, ranging from arrays of 7 to 10 drives with a capacity of several Terabytes to arrays with only two drives. With a storage unit with two drives it is possible to increase the data transfer rate by using the drives in parallel (data striping) or increase the capacity by continuing on the second drive when the first tape is full (cascading).

The output data rate of the PCI should be at least 32 MB/s (multiple field centre processing). This data rate is to much for most removable storage media therefor the data must be split to several independent storage devices. The most obvious choice is to split the PCI several independent units each processing only data from several correlator boards.

3	PROPOSED PCI ARCHITECTURE

3.1	Proposed Architecture

Based on the requirement analysis one possible solution for the PCI is to separate it into several independent units. Because the correlator consists of eight independent correlator segments, an obvious choice is to separated the PCI in eight independent PCI segments. In this case each PCI segment has to handle input coming from four correlator boards. The output from each PCI segment will be a SCSI interface for connecting to a general SCSI tape device.

Because two correlator segments reside in one correlator crate, it must be possible for two PCI segments to reside in the same VME-rack at the bottom of a correlator rack.

Building a PCI segment with four C40 communication ports as inputs has the advantage that there are commercially available DSP boards which can handle four C40 comm ports. Accompanied by a board or module providing a SCSI interface this could provide all the processing power for a PCI segment. By connecting one correlator segment to a DSP board, it is also possible to combine correlator products from different correlator boards (more lags for fringes). Furthermore the output data rate is kept to an acceptable limit. The aggregated data input rate for a PCI segment is then about 40 MB/s. With an reduction ratio of 4 this could meet the 10 MB/s storage transfer rate for a removable tape device.

After researching available hardware it is found that a one board solution is not feasible for a PCI segment, i.e. there is no suitable hardware available integrating processing power and a SCSI controller on one VME board. The most useful solution is to separate the PCI segment into a processing board and a data recorder board. The advantage of this solution is that there is better separation between the processing part and the recording part.

Available hardware options also showed that the connection between processing board and recorder board is best performed by C40 communication ports. Other options where also available (e.g. Raceway) but restricted other operations in certain configurations. The advantage of using a data recorder board with four C40 communication ports as input is that it could be connected directly to the correlator segment. This is especially useful during development, data storing can be developed independent from the processing part.

3.2	Synchronization

The RT system in the PCI is intended to operate similar to the RT system in the correlator. This can be achieved by using the same software for the RT system in the PCI and in the correlator. This software requires some external events (VME interrupts) for proper operation and system synchronization.

In the correlator these interrupts are generated by the Control Board. One of the functions of this board is to regenerate the BOCF and the SYSTICK signals for the correlator boards. The control board also generates VME interrupts for the RT system.

For synchronization of the PCI with the EVN correlator it is required to regenerate the VME interrupts based on the BCOF and the SYSTICK signals of the correlator. In order to do this a VMEbus interface is required. The control board in the correlator not only contains the logic for the VMEbus interface but also for the VME interrupt generation. Based on this logic it is possible to design a small PCI control board which can regenerate the required interrupts. The BOCF and SYSTICK signal can be obtained directly obtained from the correlator backplane and used as inputs for the PCI control board.

3.3	Hardware Interfaces

3.3.1	PCI Inputs

Source:	Correlator

Number of signals:	32 channels (fewer for prototype)

Signal levels:	TTL (?)

Signal Format:	Byte wide serial

Data Format:	Texas Instruments C40 blocks with data descriptor

Data Rate (burst):	20 Mbyte/s/channel max

The maximum data input rate is 20 kword (80 kbyte) per 9.75 msec. That is about 8205 kbyte/sec for each input channel.

Data Rate (sustained):	approx. 10 Mbyte/s/channel max

This results in an overall input rate for the PCI of 320 MB/s.

3.3.2	PCI Outputs

Destination:	SCSI tape device

Number of signals	8 channels

Output type	SCSI interface

Data Rate (burst)	40 Mbyte/sec per channel

3.3.3	Control Interfaces

Source/Destination:	CCC

Function:	Input - commands and operating parameters.

Output - status indications.

Interface standard:	Ethernet

Connection Hardware:	Thin wire. ???connectors

Protocol:	TCP/IP

Source/Destination:	DDD

Function:	Input - commands and operating parameters.

Output -processed correlator data.

Interface standard:	Ethernet

Connection Hardware:	Thin wire. ???connectors

Protocol:	TCP/IP

3.3.4	Synchronization Interfaces

Source/Destination:	correlator backplane

Function:	Input - interrupt signals

Interface standard:	none

Connection Hardware:	cable connection possibly

Protocol:	TTL ?

3.4	Installation Requirements

Available space?

Proximity of inputs, supplies, LAN connection

Maximum power dissipation, available cooling facilities.

The PCI will be placed in a VME rack below the correlator boards.

3.5	Electrical Requirements

The PCI shall include an integral power supply providing all necessary voltages from a single phase, 220/240Vac/50Hz input.

3.6	EMC Requirements

3.6.1	Emissions

3.6.2	Susceptibility

3.7	Safety Requirements

{who goes to jail if someone is injured by this equipment?}

3.8	Environmental Requirements

The PCI shall continue to perform in compliance with this specification under the following conditions:

Temperature	Operating:	0C to +45C

Storage:	-20C to +65C

Altitude	Operating:	10,000 ft

Storage:	50,000 ft

Humidity:	5% to 95% (non-condensing)

4	INITIAL HARDWARE DEFINITION

4.1	Hardware selection

4.1.1	Processing board

For selecting a processing board two major requirements must be accomplished. The board must accept input coming from C40 communication ports and it must be able to perform all the required processing.

Because of the requirement of C40 communication input ports a SHARC based DSP board is not an option. The available SHARC based boards have no (or limited) standard options to interface with C40 communication ports.

The easiest way to get a set of C40 communication ports is to use a C40 based DSP board. The only problem is that there is a possible restriction on the processing capabilities. The allowed processing time and the C40 benchmarks show that there is a possible restriction in a worst case situation.

Complex Fast Fourier Transform (integration interval 15.625 msec)

products	lags	allowed time	bench marks (C40)
256	32	61 usec	?
128	64	122 usec	57 usec
64	128	244.1 usec	133.4 usec
32	256	488.2 usec	306.2 usec
16	512	976.5 usec	692.1 usec
8	1024	1953.1 usec	1557.8 usec
4	2048	3906.2 usec	?

Real Fast Fourier Transform (integration interval 9.75 msec)

products	lags	allowed time	bench mark (C40)
256	64	38 usec	30.1 usec
128	128	76.1 usec	67.3 usec
64	256	152.3 usec	152.5 usec
32	512	304.6 usec	345.3 usec
16	1024	609.3 usec	776.1 usec
8	2048	1218.7 usec	?
4	4096	2437.5 usec	?

This implies that one C40 can not process all the data coming from a correlator board. A possible solution is to use two C40 DSPs to process the data coming from one correlator board. There is an octal C40 boar available from Pentek, the model 4285. This board could be able to process the data coming from an entire correlator segment, i.e. four correlator boards. The subdivision of the workload between two C40 DSPs requires however a large software effort.

There is a second possible option. The benchmarks of Pentek, based on numbers from Texas Instruments, show that the new C6x based DSPs have far more processing power than a C40 DSP.

Pentek (TI) benchmarks

TMS320C6201	TMS320C6701	ADSP-21060	TMS320C40
Clock speed	200 MHz	167 MHz	40 MHz	50 MHz
1 K complex FFT (radix 4)	66 usec	108 usec	460 usec	1890 usec
Filter tap	5 nsec	6 nsec	25 nsec	40 nsec

The disadvantage of a C6x DSP is that there is no standard C40 communication port compatible port available on the chip. Pentek has add on adapters available for their C6x boards to provide these C40 communication ports. The Pentek Model 4291 configurable quad TMS320C6701 Processor VME board can be equipped with two Pentek Model 6223 Comm port adapters, to supply the eight needed C40 communication ports. With these modules each C6x DSP will have two C40 comm ports, one for input and one for output. The advantage of this board is that each DSP has larger private memory resources and the performance of the DSP is much higher than for C40 DSP's.

Resume there are two possibilities for the processing board.

Solution 1

Pentek Model 4285 Octal 'C40 board	$ 33.745

Model 4285-007-003

Solution 2

Pentek Model 4291 Quad TMS320C6701 processor VME board	$ 20.619

2 x Pentek Model 6223 'C40 Comm port Adapter VIM-2 Module	$ 2.486

Because the C40 board is more expensive and offers less processing power it is recommended to go with the C6x based board. This requires however some additional development tools.

4.1.2	Recording board

Due to the fact that the processing boards outputs are again C40 communication ports, the recording board requires these ports as inputs. There is also a SCSI interface for output needed. Because there is no one board solution available, the only solution is to use a baseboard with mezzanine interfaces.

For the recording board are also two options possible.

The first is using a Pentek Model 4284 C40 MIX baseboard with a Pentek Model 4260 MIX SCSI-2 controller. The disadvantage of this solutions is the MIX interface. The only MIX modules and baseboards are available from Pentek and the bandwidth of the MIX interface is restricted to 40 MHz. The advantage of this board is that Pentek has software libraries available for performing data streaming to the SCSI controller.

A more convenient solution is to use a PMC mezzanine interface instead of the MIX interface. PMC is a IEEE standard for mezzanine modules (see Appendix B). There are PMC SCSI controllers available from different manufacturers. There is also a C44 PMC module available from Pentek (Model 7110) providing the necessary C40 comm ports to the recorder board. In that case only a ly a PMC carrier board for VME is needed. The VMETRO Midas 20 carrier board can be used for this.

The advantage is that the maximum transfer rates between the C40 processor and the SCSI controller are much higher (max 132 MHz) and it is quite easy to replace the SCSI interface with a fibre channel interface in the future. Fibre channel interfaces are much faster than SCSI and more and more storage devices are equipped with fibre channel interfaces.

The latter solution requires however a little more software programming effort because PCI programming must be implemented.

Solution 1

Pentek Model 4284 C40 Mix baseboard	$ 6.840

Pentek Model 4260 MIX SCSI-2 controller	$ 3.120

Solution 2

VMETRO Midas 20 PMC carrier	f 3475

Pentek Model 7110 C44 Comm port bridge PMC module	$ 4.993

SCITECH SCSI875 PMC module	$ 550

The second solution is not only more flexible but also cheaper.

4.1.3	Control module

For system synchronization there is also a interrupt generator required based on the BOCF and SYSTICK signals of the correlator. The VME bus interface logic is already available in the EVN correlator control board. This logic can be used, with minor modifications, on a plug in module in the PCI VME backplane.

It is decided to design a small plug in module containing only the VMEbus interface of the EVN correlator control board. This control module receives two input signals (BOCF and SYSTICK) from the correlator backplane. This control module is to be placed in a connector on the rear side of the J1 backplane of the VMEbus. In this way it will act like an ordinary VME board with the exception that it is located at the rear side of the backplane, this simplifies mechanical construction.

The VMEbus interface EPLD XILINX XC73108-15 contains a 20 bit register. This register can be read and/or written by a normal data access. The VMEbus register listens to register address 0. This register is also returned as interrupt vector as part of the interrupt acknowledge cycle. The bit assignment in this register is.

0-2	IRQSOURCE	The 3 interrupt inputs; bit 0 is the regenerated BOCF signal of the interrupt cycle control module (INCM) (RBOCFSYNCI), bit 1 is the regenerated SYSTICK (RSYSTICK) and bit 2 is the integration ready signal of the integration cycle control module (ICCM). A positive edge of the input signal will set the corresponding bit. When the VMEbus interrupts are enabled, IRQSEL has another value then 0, then the bits are cleared after the interrupt acknowledge cycle. A VMEbus read do not affect these bits. When, at the other hand, the VMEbus interrupts are disabled, IRQSEL=0, then the bits are cleared after a VMEbus read.

3-7	IVECTOR	The interrupt base vector. The 5 bits of the interrupt base vector are programmable by the VMEbus. With the 3 IRQSOURCE bits this bits form an interrupt vector.

8-10	IRQSEL	The interrupt level select bits. The 3 bits determine the level of the VMEbus interrupt. IRQnr. = IRQSEL0-2. The VMEbus interrupts are disabled with interrupt level 0.

11,12,13	IBOCF,ISYSTICK and IINTRDY

The interrupt enable bits of the interrupt inputs. The VMEbus interrupt are, for the 3 interrupt inputs separately, to enable. The status of the disabled inputs can still be read from the register. How the reset of the inputs takes place still depends on the IRQSEL setting.

14-19	IDENT0-5	The VMEbus interface has 6 available input lines that can be read from the VMEbus register. These lines are used for a unique identification code of the control board.

The control board only responds to a 32 bit interrupt acknowledge cycle (D32) and returns a 20 bit STATUS/ID on D00-D31.

4.2	Construction

The Post Correlator Integrator is VME based. All VME boards involved measure 6U x 160 mm.

4.2.1	Physical

The Post Correlator Integrator is constructed from four independent units. Each unit is placed in a standard VME rack and will be located below the correlator VME rack in the correlator crate.

Each PCI unit consists of two PCI segments and a VME System Controller.

4.2.2	Internal Interconnections

With in each PCI unit there are several internal connections. All boards are connected via a standard VME64 backplane. This backplane is only used for board configuration and retrieving status information. All data transfers between the processor board and the recorder board is performed via C40 communication ports on the front panel.

4.2.2.1	J1 Backplane

The J1 connector is a 96 pin DIN style connector conform the IEEE std 1014 for VME.

4.2.2.2	J2 Backplane

The J2 connector is a 96 pin DIN style connector conform the IEEE std 1014 for VME.

4.2.3	External Interconnections

{route for connections in and out}

There are several external connection required.

Connection between correlator boards (FP) and processing board (FP)

Connection between processing board (FP) and recording board (FP)

SCSI connection between recording board (FP) and tape device.

Connection of BCOF and SYSTICK from EVNNFRA backplane to PCI control module (rear of VME backplane).

4.2.4	Connector types.

Connector Reference	Function	Source/ Destination	Number of Ways	Connector Type	Mating Connector Type
C1	processing input	correlator board C40 comm port	unidirectional
C2	processing input	correlator board C40 comm port	unidirectional
C3	processing input	correlator board C40 comm port	unidirectional
C4	processing input	correlator board C40 comm port	unidirectional
C5	processing output	C9	unidirectional
C6	processing output	C10	unidirectional
C7	processing output	C11	unidirectional
C8	processing output	C12	unidirectional
C9	recorder input	C5	unidirectional
C10	recorder input	C6	unidirectional
C11	recorder input	C7	unidirectional
C12	recorder input	C8	unidirectional
C13	data output to storage	SCSI device	bidirectional

4.3	Supply Rails

4.3.1	Allocation

Regulated DC supplies shall be derived from a common ac supply and distributed to all modules via the VME J1 backplanes in accordance with IEEE std 1014. Power supplies shall conform with the following specification:

Mnemonic	Description	Allowed variation	Ripple/Noise below 10MHz (pk- pk)
+5V	+5V dc	+0.25V/-0.125V	50mV
+12V	+12V dc	+0.60V/-0.36V	50mV
-12V	-12V dc	-0.60V/+0.36V	50mV
+5V STDBY	+5V dc standby	+0.25V/-0.125V	50mV
GND	ground	reference

The following J2 connector pins shall be reserved for additional power connections:

A2,B2,C2,D2,E2,A38,B38,C38,D38,E38:- +5V dc

A3,B3,C3,D3,E3,A37,B37,C37,D36,E37:- GND

{provisional list}

4.4	Power budgets

Model	#	+5 V (A)	+12 V (A)	-12 V (A)
HP-743	1	7.7	0.1 A	0.1
M20-Midas 20 - 2 slots PMC carrier	2	2.4	0.05 A	0
C44 comm port bridge	2	3	0	0
Pentek Model 4291 Quad TMS320C6701 processor VME board

full quad option	2	8	0.5	0.5
Pentek Model 6223 'C40 Comm port Adapter VIM-2 Module	4	0.25	0	0
PMC SCSI controller	2	0.8	0.1	0.1
total	37.1	1.4	1.3

3.5	Power Supply and signal transmission/grounding

Each Module shall be responsible for its own power supply filtering and de-coupling.

Ground distribution on modules and motherboards shall be via ground planes with separate Digital (0VD) and Analogue (0VA) planes if appropriate.

Connector loading permitting, each signal shall be accompanied by a dedicated ground connection.

3.6	Cooling

3.7	Additional Supplies

For development some adaptions to the infrastructure are required. A development system is required containing a correlator prototype to be used in combination with the PCI under development. There is also a network connection required to the DAW17 server. For the hardware emulator there is also a PC required next to prototype system, this computer should also have a network connection to enable remote debugging.

3.8	Control Computer

{software requirements for the Single Board Computer}

{CCC message formats}

3.9	DSP Module

{DSP algorithms}

4	PROJECT DOCUMENTATION AND CONTROL

4.1	Documentation

{allocate a documentation numbering scheme}

4.1.1	Media

The following media/formats shall be used:

Non-editable text and drawings:-	Postscript format,

Editable drawings:-	Autocad level 10 or DXF,

PCB artwork:-	Gerber,

Schematics:-	ViewLogic

Text:-	WordPerfect

4.2	Change Control

4.2.1	Hardware/Firmware

4.2.2	Software

{software version control?}

5	TESTING

5.1	Test Philosophy

5.2	Test methods

5.3	Test equipment

{anything we have to buy?}

5.4	Test plan

A test plan will be generated which will define all the tests to be carried out and the expected results.

A.	ORDERING INFORMATION

Hardware

Real-Time system

Triple P

Postbus 245

4130 EE Vianen

tel: 0347-353333

fax: 0347-353332

Qty	part number	description	price / qty.	total
1	W-A4261A	HP 9000 Mdl 743rt VMEbus Single Board Computers	f 20.000	f 20.000
1	W-A4261A-203	100 MHz 743, no graphics
1	W-A4264A	16 Mb RAM card for 743
1	W-A4303A	LAN cable for 743
1	A2636-61601	RS 232 kabel, 9pins-9subD

Processing board

Connect BV.

Ekkersrijt 4601

5692 DR Son

tel: 0499-460706

fax: 0499-460737

Qty	part number	description	price / qty.	total
1	Pentek Model 4291

full quad option	Quad TMS320C6701 processor VME board	$ 20.619	20.619
2	Pentek Model 6223	'C40 Comm port Adapter VIM-2 Module	$ 1243	2486
1	Pentek Model 7110	Single 'C44 Coprocessor PMC module	$ 4.993	4.993
17.5 % BTW	4982
total	$ 33.455

Recording board

Arcobel

Postbus 344

5340 AH Oss

tel: 0412-653265

fax: 0412-630635

Qty	part number	description	price / qty.(inc BTW)	total
1	M20	VMETRO Midas 20 PMC carrier	f 4517	f 4517,-

SciTech Inc

7878 Big Sky Dr., Suite A

Madison, WI 53719

tel : (608) 833-7877

fax: (608) 833-8719

Qty	part number	description	price / qty.(inc BTW)	total
1	SCSI875-DF	SCSI-2 PMC controller	$ 646	fl 1292,-

VME-Rack

Geveke electronics

postbus 652

1000 AR Amsterdam

tel: 020-5861595

fax: 020-5861985

prototype VME rack 160 mm

Qty	part number	description	price / qty	total
1	20817-032	Printkaartrek 6HE ten behoeve van Eurokaart 160 mm diep	f 129,60
2	30817-031	Dekplaat 6HE, geeloxeerd
2	30819-594	Schroefdraadstrip M2,5mm
4	60817-061	Isoleerstrip	f 2,90
40	60817-103	Printkaartgeleider ten behoeve van Eurokaart 160 mm diep
1	23000-481-10	VME backplane J1/J2 dubbelle connector slot 21	f 2471,70
price : Dfl 2600,-

Mulder-hardenberg BV

Westerpark 1a

2012 JL Haarlem

Power supply

Qty	part number	description	price / qty	total
1	137-010000	VERO - TRIVOLT PO500	fl 1688,-	fl 1688,-

Development Software

Development tools

Qty	part number	description	price / qty	total
1	13-070	GDSP C/C 3X/4X PC	fl 4360	fl 4360
1	17-604	RSTSP 1 YR/GDSP DBG FLT PC	fl 845	fl 845
1	05-002	SUMMIT-510/PCI EMU/JTAG	fl 8545	fl 8545
1	13-956	WM/GO Network drivers	fl 865	fl 865
1	13-074	GDSP C/C 6X PC	fl 4360	fl 4360
1	17-606	RSTSP 1 YR/GDSP DBG C6X PC	fl 845	fl 845
1	11-206	TI CMP/ASSM/LNK C62X PC	fl 3920	fl 3920

B.	PMC - The New Super Mezzanine Standard

The Multibus, VME and Futurebus+ suppliers have joined forces to agree on a common standard for mezzanine boards. The result is PMC (PCI Mezzanine Card) - a mezzanine bus based on the well established high performance PCI (Peripheral Component Interconnect) specification. PCI is now used by most high performance PC system suppliers and add-in card vendors. Hence, it is very well supported, low cost and readily available.

What is PCI

PCI was developed by Intel as a very high performance local bus to provide a means of inter-connecting components together on a board but with no external access. Its purpose was to provide a simple low-cost way to add high performance peripheral components like graphic controllers and I/O devices to a CPU.

Following the initial release of this interface, a modified definition was derived which provided an external interface - this became known as the PCI bus. This bus allows for PCI boards to be plugged into the PCI bus connector. PCI provides many features including data transfer rates of 132Mbytes/s (264Mbytes/s for 64-bits), support for a system similar to Multibus II's Interconnect and 3.3V interfaces.

Mezzanine Problems ... and Solutions

Mezzanine cards have long been a popular method of adding additional or specialized I/O to processor boards. In the Multibus II market, there already exists standards such as iSBX and MIX from Intel, but these interfaces are relatively low performance and do not have a wide multi-vendor support. Concurrent Technologies overcame the performance problem by adding high performance I/O directly onto the board therefore achieving very high data transfer rates and low latency between the CPU, Memory and I/O. This is much better than using either of the existing mezzanine standards because the processor does not have to sit idle (waitstates inserted) waiting for these slow expansion interfaces to respond. With new CPUs, like the Pentium a lot of CPU time can be wasted with these slow interfaces. However, if a very fast expansion interface was available, that did not force the CPU to sit idle, then high performance mezzanine systems could be built using this expansion interface. PCI provides such an expansion interface and with its wealth of support from any different processor and peripheral component manufacturers as well as PC vendors, the bus is an ideal choice for use as a low cost mezzanine system.

The PMC Standard

PCI boards have a form-factor very similar to that of the conventional AT (ISA) boards so that they remain compatible with existing PC packaging. In a PC system, PCI boards (like ISA boards) are mounted at a 90 to the board - as this would occupy about 5 (Multibus II or VME) slots! However, by mounting the PCI card in a plane parallel to the Multibus II or VME board and using different low profile connectors, a PCI board can be fitted onto Multibus II or VME boards - and within a single slot. This connection system together with PCI interface is called PMC.

The group of companies defining the PMC specification wanted to use as many existing standards as possible. Therefore the PCI (Version 2.0) electrical and logical specification was selected together with the IEEE's proposed CMC (Common Mezzanine Card) standard. CMC defines the size of the slave mezzanine cards, the type of connector to be used and the position of the connectors on the master board

and on the slave board. Multiple 64-pin low profile connectors are utilized. The PMC standard defines which connector pins are used for which PCI signals; in addition it defines 64 of the connector pins for use

I/O signals. The PMC standard is known as the IEEE P1386.1.

A single size PMC module measures 74mm x 149mm. Two such modules could therefore fit side by side on a Multibus II or VME motherboard. Depending upon the specific implementation of a slave PMC board, the user I/O can be accessed either through the P2 connector or directly through the front panel of the motherboard.

Benefits

As an IEEE standard, PMC assures users that any host or module complying with the standard will function with any other module or host designed to the standard. This offers users flexibility to mix and match different host cards and modules. PMC is an open standard. It brings to Multibus II and VME a wealth of I/O products and capabilities which have not been readily available before.

For high performance Multibus II users, it offers an extremely high performance I/O interface for their specialized I/O requirements. More graphics options will be available. And yet, since the boards will essentially have originated from the large volume word of PCs, the price of these modules should be relatively low.

Mezzanine cards will continue to provide a method of customizing and optimizing the use of Multibus II and VME motherboards. PMC brings mezzanine technology up to date.