JOINT INSTITUTE FOR VLBI IN EUROPE

DOCUMENT NUMBER:

PROJECT:	RTD ERB4062PL975013

ISSUE:	DRAFT

DATE:	990122

POST CORRELATOR INTEGRATOR

HARDWARE SPECIFICATION

i.	AMENDMENT RECORD

DATE	ISSUE	DESCRIPTION	PAGES AFFECTED

12-04-98	draft	document creation

ii.	TABLE OF CONTENTS

Ref	Section	Page

i.	AMENDMENT RECORD	2

ii.	TABLE OF CONTENTS	3

1	INTRODUCTION	4

2	REAL TIME SYSTEM	4

3	PROCESSING BOARD	4

4	DATA RECORDER BOARD	4

5	PCI control board	4

5.1	VMEbus data transporter	5

5.2	VMEbus interrupter	7

5.3	VMEbus register (0)	7

1	INTRODUCTION

Operating environment for the Post Correlator Integrator

PCI	Post Correlator Intergrator

PCI unit	Subpart of the PCI residing in a VME rack inside the correlator crate.

PCI segment	Smallest entity providing PCI functionality. It consists of a data processing board and a data recorder board with a SCSI connection. It handles input from four correlator boards.

What is actually considered as being the PCI? The existing architecture has the following parts; the correlator, the CCC and the DDD. From the CCC and DDD point of view is the correlator constructed out of four correlator segments. The inputs for the PCI coming from the 32 correlator boards is obvious. If the actual operators at the CCC and the DDD are considered as the actual inputs to the system, than the CCC and DDD software is part of the PCI project. This seems a too general approach for the PCI project. A second approach would be to consider the CCC and the DDD as inputs to a PCI unit. This reduces the PCI project to smaller proportions leaving the CCC and the DDD to access four independent PCI units. A second consideration is the role of the System Controller that is part of the PCI segment.

2	REAL TIME SYSTEM

For the System Controller in the VME rack is a HP model 743 real-time system used. This Real-Time system is the connection between the PCI unit and the CCC and the DDD. Its main tasks are to boot the two PCI segments inside the VME rack and to configure the PCI segments for operation and to acknowledge the VME interrupts on the VME bus. These interrupts perform task scheduling and synchronization in the real-time software. These interrupts are generated in the control board in the correlator rack. It has to be checked if a proper interrupt acknowledge can be performed.

3	PROCESSING BOARD

For the processing board a Pentek model 4291 board is used.

The main tasks for the processor board are to receive the data coming from the correlator boards. Process this data according to its configuration. The processed data is passed on to the recorder board via C40 communication ports.

4	DATA RECORDER BOARD

The data recorder board main task is to convert four C40 communication ports into one SCSI output. This is created by two PMC modules. One PMC C40 comm port bridge module and a PMC SCSI controller. The C40 module can act as master on the PMC bus and program the SCSI controller directly. Therefor these modules can reside on a simple VME carrier board with no additional processing power.

(Based on module documentation, not confirmed by Pentek)

On the C40 module the following tasks need to be performed. Data collecting from four C40 comm ports, programming the SCSI controller and transferring the data to the SCSI controller.

The PCI modules need to be configured and booted by the real-time system. After this the modules are supposed to operated autonomously.

5	PCI CONTROL MODULE

The PCI control board is a largely reduced version of the EVNFRA control board. Its only use is to regenerated the interrupts for the BCOF and the SYSTICK. Compared to the EVNFRA control board only the VMEbus module of this board is needed. It must however be checked if there are other register expected to be present on the control board.

It might be possible to just take the VMEbus module from the EVNFRA control board and use this as the PCI control board. The only change required will be the addressing of the additional registers.

The VMEbus interface performs the interfacing tasks between the VMEbus and the local circuits on the board. The VMEbus interface can only act as a slave interface. It responds only to 32 bit addressing modes (A32) and is capable of handling data transfers of 32 bits wide (D32). The VMEbus interface can also act as an interrupter. There are 3 inputs available for doing interrupts. The required interrupt vector is supplied by the interface. The interrupt vector consists of 3 bits telling which interrupt source has made the interrupt and a 5 bits unique word that tells from which board in the system the interrupt is coming from.

The VMEbus interface is built up around a XILINX EPLD XC73108-15PC84. Almost the whole VMEbus interface fits in one big EPLD. The board address and base address decoding is done outside the EPLD, for a smaller and cheaper plastic package.

The VMEbus interface consists of two main parts the VMEbus data transport and the VMEbus interrupter.

5.1	VMEbus data transporter

The VMEbus interface can only act as a slave interface. It responds only to 32 bit addressing modes (A32) and is capable of handling data transfers of 32 bits wide (D32). For supporting this addressing mode different logical components are required to complete the VMEbus data transport interface.

Board address decoder

input:

BOARDA	8 bits	8 bits board address from external DIP switch

A[31:24]	8 bits	8 address lines from VMEbus

output

AMATCH1	1	active when address match occurs

This is simply an comparator identifying a correct board address.

Base address decoder

input:

BASEA	19 bits	19 bits board address from external DIP switch

A[23:5]	19 bits	19 address lines from VMEbus

output

AMATCH0	1	active when address match occurs

This is simply an comparator identifying a correct base address.

It might be required to extend this base address with address lines A[4-2] when the additional EVNFRA control board registers are not used.

A32 cycle decoder

input:

AM[5:0]	6 bits	Addres modifier bits

IACK	1	interrupt acknowledge signal from VMEbus

output

EXAMMATCH	1	active when the VMEbus cycle is a correct addressing mode and not an interrupt acknowledge cycle.

According to suggestion 2.1 of the VMEbus specification A32 slaves with D32 capability should support addressing modes : 09, 0A, 0D, and 0E

D32 cycle decoder

input:

DS0	1	data strobe

DS1	1	data strobe

A1	1	this address line should be 0 for a D32 cycle

LWORD	1

output

D32CYCLE	1	active when a D32 access occurs

The only possible D32 cycle is a quad byte read or write cycle. For quad byte cycles DS0,DS1,A1 and LWORD must be 0 (and A0 also).

Addressing lines

A01-A31	address lines

AM0-AM5	address modifierA32 slave with D32 capability should respond to address modifiers 09, 0A, 0D, 0E

DS0*	data strobe

DS1*	data strobe

LWORD*

Data lines

D01-D31

Control lines

AS*	address strobe	A falling edge on this line informs all SLAVE modules that the address is stable and can be captured.

DS0*	data strobe

DS1*	data strobe

BERR*	bus error

DTACK*

WRITE*	read/write

SUGGESTION 2.1:

Where SLAVES are manufactured with a programmed device (e.g. a PROM or a FPLA) installed in the socket, program the device so that the SLAVE responds to the following AM codes:

A16 SLAVES with D08(0), D08(EO), D16, or D32 capability: 29, 2D

A24 SLAVES with D08(0), D08(EO), D16, or D32 capability: 39, 3A, 3D, and 3E

A32 SLAVES with D08(0), D08(EO), D16, or D32 capability: 09, OA, OD, and OE

A24 SLAVES with BLT capability: 3B, 3F

A32 SLAVES with BLT capability: OB, OF

The mnemonics A16, A24, and A32 are defined in Table 2-9. The mnemonics D08(0), D08(EO), D16, D32, and BLT are defined in Tables 2-10, and 2-11.

DS0 and DS1

The functions and requirements of DS0 and DS1 are based extracted from the VMEbus specification.

2.2.4.2 DS0* And DS1*

In addition to their function in selecting byte locations for data transfer, as described in Section 2.2.1, the data strobes also serve additional functions. On write cycles, the first data strobe failing edge indicates when the MASTER has placed valid data on the data bus. On read cycles, the first rising edge tells the SLAVE when it can remove valid data from the data bus.

OBSERVATION 2.7:

VMEbus MASTERS are not permitted to drive either of the data strobes low before driving AS* low. However, due to the fact that AS* might be more heavily loaded on the backplane than the data strobes, SLAVES and LOCATION MONITORS might detect a falling edge on a data strobe, before they detect the falling edge on AS*.

PERMISSION 2.5:

VMEbus SLAVES and LOCATION MONITORS MAY be designed to capture the address when they detect a falling edge on a data strobe instead of on the falling edge

OBSERVATION 2.8:

VMEbus SLAVES and LOCATION MONITORS that capture the address on the falling edge of the data strobes) need not monitor AS*.

OBSERVATION 2.9:

In order to take full advantage of address pipelining as described in Section 2.4.2, or to perform block read and write cycles, a SLAVE should capture the address on the falling edge of AS*.

2.2.4.3 DTACK*

The SLAVE drives DTACK* low to indicate that it has successfully received the data on a write cycle. On a read cycle, the SLAVE drives DTACK* low to indicate that it has placed data on the data bus.

PERMISSION 2.6:

VMEbus SLAVES MAY be designed without a driver for BERR*.

This board can be based on the VMEbus interface of the correlator control board.

5.2	VMEbus interrupter

The VMEbus interrupter on the control board can only act as an interrupt requester. The circuit has three interrupt inputs INT[2:0] available for local circuits. The three interrupt inputs can generate one interrupt request IRQ on the VMEbus. The IRQ level is programmable to all seven IRQ levels with the control bits IRQSEL[2:0]. The three interrupt inputs can be separately disabled and enabled with the control bits ENINT[2:0]. The circuit responds only to a 32 bit interrupt acknowledge cycle (D32) and returns a 20 bit STATUS/ID on D00-D31.

A positive going edge of an interrupt INT input will latch the event. When one positive going edge is detected then one IRQ output becomes active. The IRQ level depends on the IRQSEL bits in the control register. The interrupt handler has to respond with an interrupt acknowledge cycle. When it is a 32 bit interrupt acknowledge cycle, D32ACK will be high and when the three bits code on A[3:1] corresponds to the IRQ generated then OURIACKCYCLE will be true. On the positive going edge of SYNCIACKCYC, IRQREGEN is asserted and the STATUS/ID will be put on the data lines. After another SYSCLK, when the data is stable, DTACK will be asserted on the positive going edge of DSYNCIACKCYC.

The IRQ is released by the DTACK during the interrupt acknowledge cycle. This is called an ROAK release mechanism.

During an interrupt acknowledge cycle not conform our IRQ level or when there is no IRQ at all, OURIACKCYCLE will be low, In this case an active level on IACKIN will, after a short delay, be passed to IACKOUT.

5.3	VMEbus register (0)

The VMEbus interface EPLD XILINX XC73108-15 contains a 20 bit register. This register can be read and/or writen by normal data access. The VMEbus register listens to register address 0. This register is also returned as interrupt vector as part of the interrupt acknowledge cycle. The bit assignment in this register are:

0-2	IRQSOURCE	The 3 interrupt inputs; bit 0 is the BOCF signal taken from the correlator backplane, bit 1 is the SYSTICK and bit 2 can be used for an additional interrupt. A positive edge of the input signal will set the corresponding bit. When the VMEbus interrupts are enabled, IRQSEL has another value then 0, then the bits are cleared after the interrupt acknowledge cycle. A VMEbus read do not effect those bits. When, at the other hand, the VMEbus interrupts are disabled, IRQSEL=0, then the bits are cleared after a VMEbus read.

3-7	IVECTOR	The interrupt base vector. The 5 bits of the interrupt base vector are programmable by the VMEbus. With the 3 IRQSOURCE bits these bits form an interrupt vector.

8-10	IRQSEL	The interrupt level select bits. The 3 bits determines the level of the VMEbus interrupt, IRQnr = IRQSEL0-2. The VMEbus interrupts are disabled with interrupt level 0.

11,12,13	IBOCF, ISYSTICK and IADDI	The interrupt enable bits of the interrupt inputs. The VMEbus interrupt are, for the 3 interrupt inputs separately, to enable. The status of the disabled inputs can still be read from the register. How the reset of the input takes place still depends on the IRQSEL setting.

14-19	IDENT0-5	The VMEbus interface has 6 available input lines that can be read from the VMEbus register. These lines are used for a unique identification code for the control board.