Abbreviations

ITR	Internal Technical Report

WSRT	Westerbork Synthesis Radio Telescope

EVN	European VLBI Network

DXB	Data Cross Bar Switch?

DZB	is a measure application directly involving ADC subsystems.

VLBI	Very Long Baseline Interferometry. This application uses the playback units.

IVC

NRAL	Nuffield Radio Astronomy Laboratories

SERC	NASA Space Engineering Research Center

CfA	Smithdonian Center for Astrophysics

IACC	International Advanced Correlator Consortium

UNM

CJD	Correlator Job Descriptor

System part in Mark IV Data Processor

CCC (C3)	Correlator Control Computer

DPU	Data Playback Unit

SU	Station Unit

DD	Data Distributor

COR	Correlator

PCI	Post Correlator Integrator

TSPU	Test Synchronization Pulsar gating Unit

BOCF	Beginning of Correlator Frame

This is a signal generated by the station unit to identify the start of a correlator frame. I.e. the header of the frame containing parameter information of the next frame.

RBOCF

NCO	Nummerically controlled oscillator.

This oscilator is used in the correlator to control the phase rotator and the vernier delay.

Station Unit Modules

DIM	Data Input Module

TRM	Track Recovery Module

CRM	Channel Recovery Module

DMM	Delay Memory Module

DCM	Delay Control Module

PCM	Phase Calibration Module

SUIM	Station Unit Interface Module

MRX	Multiplexed Receiver

MTX	Multiplexed Transmitter

TSPU modules

TSPM	Test Synchronization Pulsar gating Module

CLKM	Clock Module

Recommended readings

The following documents provide information on the functionality of the station units and the correlator.

The HAYSTACK correlator chip functional description

A.Bos W.H.Aldrich, A.R.Whitney

NFRA-ITR 207

MARK IV memo 237

Correlator board hardware specification

Joel Goodman

MARK IV memo 191.1

Functional Description of the EVN-Mark IV Data Processor

Jean Casse

draft document

Action to be taken

Define operational tasks of 'actors'

Search for useful OOAD tools

Research different output device possibilities

Generate descriptions of PCI functionality

Notes

correlation function information

The correlation function information is produced by the COR. The correlator hardware is flexible, it's functionality is characterised by five parameters;

•	baseband factor b

•	polarization factor p

•	recirculation factor r

•	the number of stations s

•	the number of spectral frequency points f

What's the difference between a station and polarization?

The correlator calculates a correlation function per baseband for all station/polarization combinations.

What is the baseband and how many are there?

XF correlator

An XF correlator calculates the auto- or cross correlation function of its input signals.

The correlator has the capacity to calculate all the correlations between 16 antennas (stations) in all four polarizations for a total bandwidth of 160 (128) MHz.

The Playback unit

The playback subsystem consists of 16 stations (antennas) with 32(64 for 2 headstacks) subband(tracks) signals each. Each track replaying at 16 Mbit/sec, i.e. 8 MHz (2 bit) per track. For a total of 1024 Mbit/sec per playback system(station).

The Station Unit

A station unit consists of:

2 Data Input Modules (DIM)	A DIM module can route 32 tracks to the Track recovery modules.

8 Track Recovery Modules (TRM)	Each TRM recovers the clock from 8 tracks. The clock recovered data is placed in memory to determine the sequence in which individual frames from the various tracks are output in order to properly reconstruct the original data streams.

1 Channel Recovery Modules (CRM)	The track data is converted to stream channel data by the CRM. The Station unit can handle only a maximum of 16 channels. This implies that tracks are combined to channels or if each channel is a track, all channels have to be handled in two runs. In practice there seems to be only one CRM present in the station unit (design change?).

2 Delay Memory Modules (DMM)	The output of the CRM is stored in the delay memory modules. The DMM is controlled by the Delay Control Module to produce synchronized data.

controlled by

1 Delay Control Module (DCM)

1 Phase Cal Module (PCM)

1 SU Interface Module (SUIM)

1 VME real time processor (PSOS+)

Questions that need to be answered

What is the DZB application? In a DZB application the antennas are directly connected to the correlator. It uses a much lower output rate of once every 10 seconds than the VLBI application. This is due to the smaller distance between the antennas. In that case interference patterns do occur less frequently and therefor a lower output rate (32.678 Mbyte) is required. A second difference between DZB and VLBI is that the DZB application only requires real correlation.

What is the VLBI application? In the VLBI application the antenna data is recorded on tapes and played back for analyzing. The output rate is (16.384 Mbytes) once every second.

The main difference between the two applications is interferometer based fringe phase tracking (consequence complex correlation). What is this interferometer based fringe phase tracking?

Fringe phase tracking poses the problem that phase rotation of a sampled real signal is equivalent to an in-band mixing process where upper and lower sidebands, although shifted over twice the rotation frequency, are folded on top of each other.

What is interferometry?

What is the difference between interferometry and connected element interferometry?

In connected element interferometry they antennas are at a short distance from another. So they can all be equipped with the same high precision clock signal and their outputs can be directly connected to the correlator. In VLBI the antennas are many kilometers apart. So in this case is recorded onto tapes and played back to the correlator at a central place. An atomic clock is used for synchronization of the playback signals.

What does a complex correlation look like, compared to a real (general) correlation?

Complex correlation

F(tau) = C+ iS

What is the video frequency band.

The EVN Mark IV is designed for 32 playback unit. The first implementation will have only 16 PBU operational.

This gives two different system requirements. One for the 32 PBU case, indicating the maximum system capacity. The second for the 16 PBU case, indicating the average operating condition.

32 PBU

Each PBU produces 64 tracks of data. With an bit rate of 16 Mbit/sec/track i.e. 8 MHz per track, for a total of 1024 Mbit/sec per playback unit. This data stream is passed on to the Station Unit, which reconstructs the original channel data for a maximum of 16 channels at a time. The SU transmits the output data to the Data Distributor or the Correlator via 2 multiplexed serial link modules. Each serial link module takes care of 8 SU channels at a rate of 32 MHz. Each serial link transmits the data over 4 lines defined as sign, magnitude and validity bit lines. The 4th line provides the timing with the BOCF.

Each correlator consists of two input units with 8 coax inputs each. The 64 input channels from each input unit are passed on to four correlator boards. Each correlator can have as much as 16 input serial links resulting in 128 channels.

Depending on the exact configuration the 4 correlator boards can calculate X correlation functions of the set of 64 input channels.

Questions

Known functionality at the moment

Fast data read out from correlator board

sorting

Fourier transform

Storing Data to storage media

Is there any correlator data transfer needed between PCI boards. One possible PCI configuration would be one PCI board for each correlator board. For calculation and sorting. After that the data must be stored on a media or more media? Could that be a media for each correlator board or has the data to be assembled together by another board (VME board, like in the correlator) and stored to media by this device.

MARK IV memo 237 / NFRA-ITR 207

April 1996

The Haystack correlator chip functional description

The correlator architecture uses four building blocks

•	The low level building block is a correlator block that produces a cross- or auto-correlation function from 2 or 1 input signals respectively.

•	The intermediate level building block is a 2 x 2 correlator module. One 2 x 2 module pair produces the 4 possible cross-correlations between two sets of 2 input signals. A 2 x 2 correlator module consists of 8 correlator blocks integrated in one chip.

•	The top level building block is a correlator board that contains 32 2 x 2 correlator modules. It calculates in the EVN and DZB application up to 128 cross-correlations between any combination of the 64 input signals or alternatively 96 cross- and 64 auto correlations for 16 sets of 4 input signals.

•	The correlator segment is a set of 4 correlator boards that use a common set of 64 input signals. A correlator segment can typically correlate 16 antennas (stations) in all 4 polarizations for one subband (DZB) or baseband (EVN).

The correlator chip is implemented as a full custom chip containing 8 identical correlator blocks that can be interconnected in different configurations by means of internal multiplexers. (I.e. a correlator chip is a 2 x 2 correlator module) A correlator block calculates 64 lags of the cross- or auto correlation function of two or one input signal respectively (this should be: a correlator cells calculates).

The correlator cell

The cell consists of:

•	two 16 bit shiftregisters shifting shifting in opposite direction that carry the 3 bit samples of respectively the X- and Y-signals to be correlated.

•	a total of 32 multiplier/accumulators to correlate the two times 16 shiftregister outputs.

•	A 3 level phase rotator in the X-path

•	an optional 1 sample delay in both the X- and Y-signal path.

•	a 3 sample vernier delay in the X-path to be used in combination with the phase rotator

•	one additional accumulator to keep track of the number of samples correlated.

The accumulator is 24-bit wide. This implies 32 memory addresses of 24-bit wide.

The correlator block

The correlator hardware consists functionally of:

•	two correlator cells that correlate two sample streams in complex or real mode.

•	Four input multiplexers that connect the cell inputs to one of up to 8 outputs of the cells in correlator mode.

•	A header capture module that captures the header information stored in the validity bit of the data samples.

•	A phase generator to control the phase rotators and the vernier delays in the correlator cells used in complex correlation mode.

•	A control register to store the static parameters for the block configuration.

A correlator block consists of two correlator cells and therefor has an address space of 2 x 32 = 64 memory addresses of 24-bit.

The correlator chip

The correlator chip consists of 8 correlator blocks, i.e. an address space of 8 x 64 = 512 addresses of 24 bit.

The correlator chip is functionally controlled by a number of direct control signals and via a bi-directional 24-bit wide data bus. The bi-directional data bus is used to transfer:

•	the static parameters for the chip configuration control (8 24-bit control registers)

•	the dynamic parameters for the control of the phase generators (176 16-bit wide registers, 22 for each correlator block)

•	the correlator lag and header data (608 24-bit wide registers)

The correlator board

The correlator board consists of 32 correlator chips, i.e. an address space of 32 x 512 = 16384 address of 24 bit wide.

Analysis of the requirements

1 Receive control messages from the CCC.

This requirement involves a physical connection with the CCC. It has to be determined wether this is one connection to the entire PCI or multiple connection to the sub parts of the PCI.

2 Interpreting control message to define the set of processes to be performed.

This is basically implied by the previous requirement. It has to be decided if there is a fixed set of operations to chose from or just about any possible operation of which you can select a fixed maximum number of operations.

Currently there are the following operations expected to be performed

2.1	Fourier Transform

2.2	Phase correction by complex multiplication.

This could be a vector multiplication with a coefficient vector received from the CCC.

2.3	accumulation of data sets.

3 Receive multiple channels of serial data

The entire PCI must be able to connect to the 32 correlator output serial links at the same time. So 32 PCI input serial links have to be available. These serial links have a maximum data rate of 20 Mbyte/s. It is expected that this rate will never be actually made in a continues situation. So a continuous data rate of 10 Mbyte/sec is taken.

4 Store and re-order the data as required.

The data received from the correlator can contain several channels of data

The maximum amount of data coming from one correlator board is 20 K (16 K data + 4 K header info) per 10 msec. This can be 1 channel of data or up to 256 channels of data. The minimum correlation length is 64 lags.

Timing:

9.75 msec for DZB

15.625 msec for VLBI

This is the minimum integration cycle time, i.e. no integration, for both application types. Every cycle time there is a block of 20 Kword of data available at each correlator board. This data has to be transferred to the PCI via one of the DSP serial links. This link has a possible burst transfer rate of 20 Mbyte /sec. When a cycle time of 9.75 msec is used, there are about 102 correlator blocks in a second.

The possible data to transfer is about

102 * 20 K * 4 = 8160 Kbyte/sec

The C40 serial link can handle a data transfer rate of 20 Mbyte/sec. (Newer C40 DSP's can even handle 28 Mbyte/sec). The data transferred has to be fetched from/stored to external memory, possibly using DMA. External memory access times depend on memory access times, possibly causing wait states. DMA transfer cycle counts can be calculated using:

external memory	on-chip	[(1+Cr)+1]

on-chip	external memory	[1+(2+Cw)]

With Cr and Cw the wait state count for read and write access of external memory.

Depending on the amount of wait states the DMA transfer could become the bottleneck in the data transfer.

each correlator board produces 20 Kword blocks every 9.75 (15.625) msec. Each block consists of 16 Kwords of data and 4 Kwords of additional information.

Each block can contain between 1 and 256 correlator products. This depends on the configuration of the correlator board.

There are 32 correlator boards in the 4 crate correlator, therefor 8192 correlator products can be produced every 10 msec.

I assume that the correlator configuration is fixed during one playback run. Does this imply that one configured correlator board can produce no more than 256 correlator products or is it possible to have more correlator products from one correlator board using multi 10 msec output blocks.